mirror of https://github.com/VLSIDA/OpenRAM.git
140 lines
6.0 KiB
Python
140 lines
6.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from sram_factory import factory
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from tech import GDS,layer,drc,parameter,cell_properties
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from tech import cell_properties as props
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from globals import OPTS
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class dummy_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
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self.cell = factory.create(module_type="bitcell")
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else:
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self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
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self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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self.add_mod(self.dummy_cell2)
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self.add_mod(self.dummy_cell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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else:
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from tech import custom_cell_arrangement
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custom_cell_arrangement(self)
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def add_pins(self):
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# bitline pins are not added because they are floating
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_layout_pins(self):
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""" Add the layout pins """
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# Add the bitline metal, but not as pins since they are going to just be floating
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# For some reason, LVS has an issue if we don't add this metal
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_rect(layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_rect(layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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if not props.compare_ports(props.bitcell.split_wl):
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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else:
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for row in range(self.row_size):
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for port in self.all_ports:
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for wl in range(len(wl_names)):
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wl_pin = self.cell_inst[row, 0].get_pin("wl{}".format(wl))
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self.add_layout_pin(text="wl{0}_{1}_{2}".format(wl, port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vpwr", "vgnd"]:
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self.copy_layout_pin(inst, pin_name)
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def input_load(self):
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# FIXME: This appears to be old code from previous characterization. Needs to be updated.
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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