| .. |
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configs
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golden
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00_code_format_check_test.py
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…
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01_library_drc_test.py
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…
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02_library_lvs_test.py
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…
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03_contact_test.py
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…
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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…
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_ptx_no_contacts_test.py
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03_wire_test.py
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…
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04_and2_dec_test.py
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Use factory in and_dec tests
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2020-06-22 16:55:49 -07:00 |
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04_and3_dec_test.py
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Use factory in and_dec tests
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2020-06-22 16:55:49 -07:00 |
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04_and4_dec_test.py
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Skip and4_dec test
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2020-06-23 10:08:28 -07:00 |
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04_dff_buf_test.py
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Rename dff_buf test
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2020-06-09 17:18:19 -07:00 |
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04_dummy_pbitcell_test.py
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…
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04_pand2_test.py
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Remove vertical pand gates
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2020-06-09 16:40:59 -07:00 |
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04_pand3_test.py
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Remove vertical pand gates
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2020-06-09 16:40:59 -07:00 |
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04_pbitcell_test.py
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…
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04_pbuf_dec_8x_test.py
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Add pbuf_dec gate
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2020-07-27 13:59:55 -07:00 |
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04_pbuf_test.py
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Fix pbuf test info
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2020-07-27 13:59:35 -07:00 |
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04_pdriver_test.py
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…
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinv_100x_test.py
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04_pinv_dec_1x_test.py
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DRC and LVS fixes for pinv_dec
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2020-06-12 15:23:51 -07:00 |
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04_pinvbuf_test.py
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…
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04_pnand2_test.py
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Do not run tapless unit tests
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2020-06-14 14:18:25 -07:00 |
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04_pnand3_test.py
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Do not run tapless unit tests
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2020-06-14 14:18:25 -07:00 |
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04_pnor2_test.py
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…
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04_precharge_1rw_1r_test.py
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Fix precharge offset. Move well rules to design class.
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2020-06-09 15:28:50 -07:00 |
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04_precharge_pbitcell_test.py
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04_precharge_test.py
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04_pwrite_driver_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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04_single_level_column_mux_pbitcell_test.py
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04_single_level_column_mux_test.py
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Add col mux tests for multiport
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2020-06-03 10:01:02 -07:00 |
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04_wordline_driver_test.py
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05_bitcell_array_1rw_1r_test.py
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Change bitcell array name to match
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2020-06-10 14:54:20 -07:00 |
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_local_bitcell_array_test.py
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Skip local bitcell array test
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2020-08-13 14:36:39 -07:00 |
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05_pbitcell_array_test.py
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06_hierarchical_decoder_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_decoder_pbitcell_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_decoder_test.py
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Add 1rw_1r tests
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2020-06-03 14:30:15 -07:00 |
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06_hierarchical_predecode2x4_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_predecode2x4_pbitcell_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_predecode2x4_test.py
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Add 1rw_1r tests
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2020-06-03 14:30:15 -07:00 |
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06_hierarchical_predecode3x8_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_predecode3x8_pbitcell_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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06_hierarchical_predecode3x8_test.py
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Add 1rw_1r tests
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2020-06-03 14:30:15 -07:00 |
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06_hierarchical_predecode4x16_test.py
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07_single_level_column_mux_array_1rw_1r_test.py
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Test more single level col mux configs
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2020-06-15 10:17:54 -07:00 |
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07_single_level_column_mux_array_pbitcell_test.py
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Update mirroring in port_data for bitcell mirrored arrays
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2020-06-05 11:29:31 -07:00 |
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07_single_level_column_mux_array_test.py
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Test more single level col mux configs
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2020-06-15 10:17:54 -07:00 |
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08_precharge_array_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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08_precharge_array_test.py
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Update mirroring in port_data for bitcell mirrored arrays
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2020-06-05 11:29:31 -07:00 |
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08_wordline_buffer_array_test.py
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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08_wordline_driver_array_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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08_wordline_driver_array_pbitcell_test.py
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08_wordline_driver_array_test.py
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…
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09_sense_amp_array_1rw_1r_test.py
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Add more s8 skip tests
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2020-06-10 10:14:52 -07:00 |
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09_sense_amp_array_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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09_sense_amp_array_test.py
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Update mirroring in port_data for bitcell mirrored arrays
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2020-06-05 11:29:31 -07:00 |
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09_sense_amp_array_test_pbitcell.py
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10_write_driver_array_1rw_1r_test.py
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Add u+x permissions to new tests
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2020-06-24 08:19:25 -07:00 |
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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10_write_driver_array_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_driver_array_wmask_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_1rw_1r_test.py
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Add u+x permissions to new tests
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2020-06-24 08:19:25 -07:00 |
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10_write_mask_and_array_pbitcell_test.py
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10_write_mask_and_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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12_tri_gate_array_test.py
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13_delay_chain_test.py
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14_replica_bitcell_array_1rw_1r_test.py
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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14_replica_bitcell_array_test.py
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Rename 05 test to 14
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2020-06-05 09:57:16 -07:00 |
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14_replica_column_1rw_1r_test.py
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Add new replica column test. Add more skip tests.
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2020-06-10 11:00:00 -07:00 |
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14_replica_column_test.py
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14_replica_pbitcell_array_test.py
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Rename 05 test to 14
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2020-06-05 09:55:57 -07:00 |
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16_control_logic_multiport_test.py
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16_control_logic_r_test.py
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16_control_logic_rw_test.py
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16_control_logic_w_test.py
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18_port_address_1rw_1r_test.py
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Change port_address test to 256 for riscv
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2020-06-23 15:40:00 -07:00 |
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18_port_address_test.py
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Variable zjog. 512 port address test. s8 port address working.
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2020-06-04 16:01:32 -07:00 |
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18_port_data_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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18_port_data_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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18_port_data_test.py
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18_port_data_wmask_1rw_1r_test.py
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made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test
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2020-06-23 18:16:14 -07:00 |
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18_port_data_wmask_test.py
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Update port data wmask tests
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2020-06-15 06:05:05 -07:00 |
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19_bank_select_pbitcell_test.py
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…
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19_bank_select_test.py
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19_multi_bank_test.py
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19_pmulti_bank_test.py
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…
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19_psingle_bank_test.py
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…
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19_single_bank_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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19_single_bank_1w_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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19_single_bank_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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19_single_bank_test.py
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19_single_bank_wmask_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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19_single_bank_wmask_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_psram_1bank_2mux_1rw_1w_wmask_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_psram_1bank_2mux_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_psram_1bank_4mux_1rw_1r_test.py
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Unskip 20_psram_1bank_4mux_1rw_1r_test
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2020-06-09 16:04:39 -07:00 |
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20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_2mux_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_sram_1bank_2mux_1w_1r_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_2mux_1w_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_sram_1bank_2mux_test.py
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…
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20_sram_1bank_2mux_wmask_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_2mux_wmask_test.py
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…
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20_sram_1bank_4mux_test.py
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…
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20_sram_1bank_8mux_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_sram_1bank_8mux_test.py
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…
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20_sram_1bank_32b_1024_wmask_test.py
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…
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20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_nomux_1rw_1r_test.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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20_sram_1bank_nomux_spare_cols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_nomux_test.py
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…
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20_sram_1bank_nomux_wmask_sparecols_test.py
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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20_sram_1bank_nomux_wmask_test.py
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20_sram_2bank_test.py
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…
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21_hspice_delay_test.py
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…
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21_hspice_setuphold_test.py
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…
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21_model_delay_test.py
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…
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21_ngspice_delay_extra_rows_test.py
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…
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21_ngspice_delay_test.py
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…
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21_ngspice_setuphold_test.py
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…
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22_psram_1bank_2mux_func_test.py
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…
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22_psram_1bank_4mux_func_test.py
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…
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22_psram_1bank_8mux_func_test.py
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…
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22_psram_1bank_nomux_func_test.py
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…
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22_sram_1bank_2mux_func_test.py
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…
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22_sram_1bank_2mux_sparecols_func_test.py
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SRAM layout and functional tests with spare cols
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2020-06-03 12:31:30 +00:00 |
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22_sram_1bank_4mux_func_test.py
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…
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22_sram_1bank_8mux_func_test.py
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…
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22_sram_1bank_nomux_1rw_1r_func_test.py
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Rename tests for consistency
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2020-06-19 08:53:35 -07:00 |
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22_sram_1bank_nomux_func_test.py
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22_sram_1bank_nomux_sparecols_func_test.py
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SRAM layout and functional tests with spare cols
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2020-06-03 12:31:30 +00:00 |
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22_sram_1bank_wmask_1rw_1r_func_test.py
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Rename tests for consistency
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2020-06-19 08:53:35 -07:00 |
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22_sram_wmask_func_test.py
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…
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23_lib_sram_model_corners_test.py
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…
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23_lib_sram_model_test.py
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…
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23_lib_sram_prune_test.py
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…
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23_lib_sram_test.py
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…
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24_lef_sram_test.py
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…
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25_verilog_sram_test.py
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…
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26_hspice_pex_pinv_test.py
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26_ngspice_pex_pinv_test.py
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…
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26_pex_test.py
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…
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30_openram_back_end_test.py
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…
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30_openram_front_end_test.py
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…
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50_riscv_func_test.py
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Skip riscv func test for time sake
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2020-06-26 06:50:45 -07:00 |
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50_riscv_phys_test.py
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Skip phys riscv test
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2020-06-25 17:31:23 -07:00 |
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regress.py
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Full path to skip tests file
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2020-06-10 10:23:05 -07:00 |
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skip_tests_sky130.txt
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Skip and4_dec test
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2020-06-23 10:08:28 -07:00 |
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sram_1rw_1r_tb.v
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…
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sram_1rw_tb.v
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…
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sram_1rw_wmask_tb.v
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…
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testutils.py
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Fail unit test, but mention if LVS passes and DRC fails.
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2020-06-30 16:22:44 -07:00 |
