mrg
b1bb9151c4
Reimplement off grid pins.
...
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
2022-05-02 15:43:14 -07:00
mrg
5e546ee974
New power strapping mostly working.
...
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
2022-04-05 13:51:55 -07:00
mrg
01a73b31e1
Fix power ring routing boundary bug.
2022-03-18 10:32:25 -07:00
mrg
229a3b5b3d
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
mrg
7654cd7295
Allow supply pins on m4 too
2022-03-02 16:47:17 -08:00
mrg
abac5a11ab
Move power supply stack to design
2022-02-18 15:02:45 -08:00
mrg
0c3ee643ab
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
mrg
03f87cd681
Add str function for sram_config
2021-09-07 16:49:31 -07:00
mrg
cce1305da3
Add technology parameter for library prefix during uniquification of GDS
2021-07-12 11:01:51 -07:00
mrg
0d6d707315
Reset write_size to none when it is the same as data word width
2021-07-09 12:31:35 -07:00
mrg
833b7b98ab
Conditional import of array col/row multiple
2021-06-29 11:27:54 -07:00
mrg
958f5e45bb
Add extra dnwell spacing for single port
2021-06-23 11:14:58 -07:00
mrg
c69eb47a7a
Finalize uniquify option for SRAMs
2021-06-22 16:13:33 -07:00
Hunter Nichols
a0921b4afc
Merge branch 'dev' into automated_analytical_model
2021-06-22 01:39:38 -07:00
mrg
58f8c66020
Fix disconnected spare_wen_0_0
2021-06-21 17:36:20 -07:00
Hunter Nichols
294ccf602e
Merged with dev, addressed conflict in port data
2021-06-21 17:23:32 -07:00
mrg
bb1ac1a38e
Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces.
2021-06-21 15:23:08 -07:00
mrg
f3f19aeeeb
Remove print statement
2021-06-21 15:16:36 -07:00
mrg
1ce5823df8
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2021-06-21 13:14:23 -07:00
Jesse Cirimelli-Low
56dc83de47
fix typo
2021-06-18 18:10:12 -07:00
Jesse Cirimelli-Low
2dbe928c09
fix typo
2021-06-18 18:08:57 -07:00
Jesse Cirimelli-Low
4688988434
only check dimensions on single port
2021-06-18 17:46:39 -07:00
Jesse Cirimelli-Low
2eb98083d0
Merge branch 'dev' into laptop_checkpoint
2021-06-18 14:21:39 -07:00
Jesse Cirimelli-Low
8ceece2af6
check for valid dimensions instead of recalcuating
2021-06-18 14:21:02 -07:00
mrg
693a81fa8d
Fix spare_wen IO pin names
2021-06-18 10:44:35 -07:00
mrg
1299989332
Fix single spare_wen naming
2021-06-18 08:43:21 -07:00
Jesse Cirimelli-Low
7b7c72706a
merge in dev
2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low
e775f7a355
fixed indent
2021-06-16 12:36:00 -07:00
Jesse Cirimelli-Low
2b9df2ff1f
uncomment function sim and datasheet generation
2021-06-16 11:23:27 -07:00
Hunter Nichols
4132decd32
Merge branch 'dev' into automated_analytical_model
2021-06-14 14:45:48 -07:00
Hunter Nichols
74b55ea83b
Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.
2021-06-14 14:39:54 -07:00
Hunter Nichols
7df36a916b
Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph.
2021-06-14 13:51:52 -07:00
mrg
159d0ed603
Fix s_en spacing problem.
2021-06-13 15:08:05 -07:00
mrg
cf61096936
Merge branch 'laptop_checkpoint' into dev
2021-06-04 15:22:37 -07:00
mrg
cc4c6e909b
Check if s_en exists before using it
2021-06-04 07:48:26 -07:00
mrg
4107c983e2
Make sure channel route is below s_en
2021-06-04 07:14:49 -07:00
Jesse Cirimelli-Low
6705f99855
merge in dev
2021-05-28 14:06:23 -07:00
mrg
77f221d859
Separate supply pin type from route supplies option
2021-05-28 11:55:50 -07:00
mrg
f6587badad
Improve supply routing for ring and side pins
2021-05-28 10:58:30 -07:00
Hunter Nichols
b3bcf48d2e
Merge branch 'dev' into automated_analytical_model
2021-05-26 18:42:24 -07:00
mrg
8bf37ca708
Connect dnwell taps to gnd
2021-05-26 17:38:09 -07:00
mrg
7736d3b927
Fix updated side pin option
2021-05-26 16:14:46 -07:00
mrg
e611f66767
Add dnwell
2021-05-26 16:14:16 -07:00
mrg
cc91cdf008
Add power ring pin
2021-05-26 16:14:14 -07:00
mrg
7fa6c7ce0f
Typo in wmask supply variable
2021-05-26 15:24:31 -07:00
mrg
4a8e0cdabb
Add top-level pin functionality
2021-05-26 15:04:52 -07:00
Hunter Nichols
2f4f8ca912
Fixed conflicts in delay and elmore modules on merge with dev.
2021-05-25 15:25:43 -07:00
mrg
3abebe4068
Add hierarchical seperator option to work with Xyce measurements.
2021-05-14 16:16:25 -07:00
Jesse Cirimelli-Low
0ba229afe5
Merge branch 'dev' into laptop_checkpoint
2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low
e5662180e8
single port 20 series tests running
2021-05-07 18:44:45 -07:00
mrg
Hunter Nichols
Jesse Cirimelli-Low