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Typo in wmask supply variable

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mrg
2021-05-26 15:24:31 -07:00
parent 4a8e0cdabb
commit 7fa6c7ce0f
1 changed files with 1 additions and 1 deletions
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compiler/sram/sram_base.py
+1 -1
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@@ -695,7 +695,7 @@ class sram_base(design, verilog, lef):
inputs.append("wmask{}[{}]".format(port, bit))
outputs.append("bank_wmask{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_suplies)
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts