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OpenRAM
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388 Commits

Author SHA1 Message Date
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
mrg 94c480911b ngspice raw save doesn't work with measures 2020-06-19 07:09:15 -07:00
mrg 403ea17039 PEP8 formatting 2020-06-18 14:55:01 -07:00
mrg 69f5621245 Save raw file from ngspice 2020-06-18 14:54:36 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
Aditi Sinha ef940e0dc5 Fixes for functional test of spare cols 2020-06-08 05:02:04 +00:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
mrg 4d6d6af0a1 Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
David Ratchkov c2419af2e2 Fix voltage_map names (these do not need to match pg_pin names) 2020-04-22 09:03:22 -07:00
David Ratchkov 5aea45ed69 - Fix switched disabled powers 2020-04-17 16:23:06 -07:00
David Ratchkov 123cc371be - Fix disabled power char 2020-04-17 16:09:58 -07:00
David Ratchkov 1f816e2823 - Characterize actual disabled power (read mode only) 
- Report rise/fall power individually
 2020-04-17 14:55:17 -07:00
David Ratchkov 7e36cd4828 - Write voltage_map and pg_pin 
- Remove 'when' condition on leakage power
- Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin
 2020-04-17 13:45:57 -07:00
jcirimel afcb5174ac discrete dff tests working 2020-04-11 01:19:04 -07:00
jcirimel a0eb9839ad revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
Jesse Cirimelli-Low 8b33cb519f Merge branch 'dev' into custom_mod 2020-04-03 17:05:56 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 67de7efd49 Fix syntax error. No DRC/LVS in netlist only mode. 2020-04-02 11:31:28 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
Jesse Cirimelli-Low 6e2a5d7a1a set sram output cap in characterizer to be 4x dff input cap 2020-04-01 04:24:43 -07:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
Hunter Nichols df2f981a34 Adds checks to prevent characterization of redundant corners. 2020-02-19 15:59:26 -08:00
Hunter Nichols e4fef73e3f Fixed issues with bitcell measurements variable names, made target write ports required during characterization 2020-02-19 15:34:31 -08:00
Hunter Nichols 843fce41d7 Fixed issues with sen control logic for read ports. 2020-02-19 03:06:11 -08:00
Matt Guthaus 46c2cbd2d9 Check nominal_corner_only in new corner creation routine 2019-11-29 14:47:02 -08:00
Matt Guthaus bedae87315 Only use max/min and typical corner 2019-11-29 13:31:44 -08:00
Matt Guthaus 240c416100 Remove extra print 2019-11-17 10:40:01 -08:00
Matt Guthaus 764d4da1bd Clean up config file organization. Improve gdsMill debug output. 2019-10-23 10:48:18 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus 93c89895c9 Remove unused test structures 2019-09-06 14:58:47 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00