luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,850 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

2850 Commits

Author SHA1 Message Date
Matt Guthaus abd8b0a23a Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
Matt Guthaus b71d630643 None for layer means unused. 2019-11-26 13:34:39 -08:00
Matt Guthaus 04045cf672 Fix syntax error 2019-11-26 13:24:19 -08:00
Matt Guthaus f4599b7121 Default tools are calibre except for SCMOS 2019-11-26 13:23:18 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matt Guthaus 909321326d Ignore unused layers 2019-11-26 13:21:29 -08:00
Matt Guthaus 7556872a75 OpenRAM v1.1.3 
Mucho PEP8 corrections.
Add layer-purpose to tech files.
Enable colon delimited OPENRAM_TECH list.
Add general config files for unit tests.
 2019-11-21 16:20:33 -08:00
Matt Guthaus 67a0928303 Merge branch 'dev' into tech_migration 2019-11-21 11:02:33 -08:00
Matt Guthaus 982e12be5e Increment minor version 2019-11-21 11:00:22 -08:00
Matt Guthaus 807923cbf1 Ignore pycache dirs. Fix output error message. 2019-11-21 10:11:19 -08:00
Matt Guthaus 190c5a078e Fix permissions on pwrite_driver test 2019-11-20 11:49:39 -08:00
Matt Guthaus 3364f47e56 Fix wrong supply voltage in config files. 2019-11-20 09:50:27 -08:00
Matt Guthaus 240c416100 Remove extra print 2019-11-17 10:40:01 -08:00
Matthew Guthaus cdf01c6c23 Fix test 30 for generic configs 2019-11-17 00:49:38 +00:00
Matthew Guthaus b3fb4e3183 Make unit test configs generic to tech_name 2019-11-17 00:44:31 +00:00
Matthew Guthaus b3b3cf0210 Merge remote-tracking branch 'origin/dev' into tech_migration 2019-11-17 00:15:18 +00:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
Matthew Guthaus 0b3d2fe9de Undo pdriver size change for now. 2019-11-16 19:54:39 +00:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Aditi Sinha 2c7aa5d0da Non-power of 2 address decode tentative 2019-11-15 03:59:57 +00:00
Matthew Guthaus 7e9d08206c Fix config import to be location independent 2019-11-14 20:18:18 +00:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matthew Guthaus bba6995653 Call debugger if debug_level more than 0 and an error. 2019-11-08 19:42:09 +00:00
Matthew Guthaus 8d158e9eb5 Fix lpp change 2019-11-08 15:45:25 +00:00
Matthew Guthaus 32f1cde897 PEP8 formatting 2019-11-07 16:48:37 +00:00
Matthew Guthaus 0dea153919 PEP8 formatting 2019-11-07 16:33:13 +00:00
Matthew Guthaus a2422cc8d4 Sometimes round down pdriver to fix polarity 2019-11-06 21:51:21 +00:00
Matthew Guthaus 35e65fc6f2 PEP8 wordline driver 2019-11-06 21:19:36 +00:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Matt Guthaus ecbed870c0 Remove blockage layer. 2019-10-30 06:54:11 -07:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 31825d9d77 Fix magicrc for multiple openram tech paths 2019-10-24 13:17:33 -07:00
Matt Guthaus 764d4da1bd Clean up config file organization. Improve gdsMill debug output. 2019-10-23 10:48:18 -07:00
Hunter Nichols e4b490051d Adjusted vth0 of FF and SS models in scn4m from nominal. 2019-10-07 15:26:20 -07:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus c263cfaf8d OpenRAM v1.1.1 
Fixed numerous P&R file format bugs.
Significant code cleanup and refactor.
Use new scn4m models.
 2019-10-07 12:24:07 -07:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Matt Guthaus 76ad2e68c0 Update slack invite link. 2019-10-06 17:28:06 +00:00
vagrant 67c768d22c Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
Hunter Nichols d722311822 Merge branch 'dev' into update_scmos_models 2019-10-03 13:16:32 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 1bdd9f56d6 Changed scn4m tau and parasitic model values to account for spice model changes. 2019-09-30 14:22:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus 062156fbd3 Merge branch 'dev' 2019-09-27 09:50:50 -07:00
Matt Guthaus cbbcb97a10 Merge branch 'dev' into feedthru 2019-09-27 09:42:51 -07:00
Hunter Nichols 84d41dd380 Replaced scn4m models. FF/SS are duplicated from nominal models. 2019-09-26 23:45:36 -07:00