 samuelkcrow
|
119bcb9197
|
route unused wordlines (still failing lvs)
|
2022-12-14 08:12:55 -08:00 |
|
|
samuelkcrow
|
d224c06b25
|
placement positions problem fixed, incorrect w,h calculations were the problem
|
2022-12-10 19:03:55 -08:00 |
|
 Eren Dogan
|
6a4f6cbbed
|
Move sram and sram_config to openram namespace
|
2022-12-02 15:28:06 -08:00 |
|
|
Eren Dogan
|
7396899769
|
Add empty build_graph() for dummy bitcells
|
2022-12-02 12:14:40 -08:00 |
|
|
samuelkcrow
|
68fb4e3c63
|
introduced some other bugs but scmos tiling is correct
|
2022-12-02 09:42:33 -08:00 |
|
|
Eren Dogan
|
96e57507bf
|
Add copyright check to code format test
|
2022-11-30 14:50:43 -08:00 |
|
|
Eren Dogan
|
e15454ebb9
|
Make sram_config optional for sram
|
2022-11-29 10:33:32 -08:00 |
|
|
Eren Dogan
|
fccdc3c45b
|
Use library imports globally
|
2022-11-27 13:01:20 -08:00 |
|
|
samuelkcrow
|
ac8a15acc0
|
fix get_replica_top and get_replica_left return values
|
2022-11-21 17:42:50 -08:00 |
|
|
samuelkcrow
|
5a82c45a33
|
Change how lists of BLs and WLs are named and organized for proper connection between these modules
|
2022-10-24 20:08:13 -07:00 |
|
 mrg
|
9b6eb4a120
|
Fix whitespace
|
2022-10-20 16:38:23 -07:00 |
|
|
mrg
|
8fd08916a1
|
Move is_non_inverting graph code to bitcell_base class to work with pbitcell too.
|
2022-10-20 15:16:10 -07:00 |
|
|
samuelkcrow
|
55d89fbae8
|
copy supply pins to top level in replica array, now passing tests
|
2022-10-19 17:13:54 -07:00 |
|
|
samuelkcrow
|
f9419e8ff7
|
fix self.rbls and fix handling of rbl WLs (kinda)
|
2022-10-17 20:51:42 -07:00 |
|
|
samuelkcrow
|
a1ca7c312d
|
remove grounded WLs from replica array
|
2022-10-11 11:43:26 -07:00 |
|
|
samuelkcrow
|
cfd52a6065
|
fix offsets so array ends up at 0,0
|
2022-09-26 14:24:16 -07:00 |
|
|
samuelkcrow
|
8bc3903a04
|
remove end caps from replica column (will not pass sky130 drc)
|
2022-09-26 14:23:09 -07:00 |
|
 Jesse Cirimelli-Low
|
3b02a8846d
|
sky130 rba passing :)
|
2022-09-12 16:07:00 -07:00 |
|
|
samuelkcrow
|
f1f18b3b54
|
replica code working but failing lvs
|
2022-09-07 19:32:25 -07:00 |
|
|
samuelkcrow
|
3ef52789be
|
first pass splitting replica array into capped and replica array modules
|
2022-09-07 12:39:35 -07:00 |
|
 Bugra Onal
|
25cc08db80
|
Further fixes for new verilog naming convention
|
2022-08-18 11:03:13 -07:00 |
|
|
Bugra Onal
|
a7c6406d0d
|
Changed verilog file naming convention
|
2022-08-18 10:36:54 -07:00 |
|
|
Bugra Onal
|
1a23d156c0
|
remove references to bank_sel
|
2022-08-18 10:33:46 -07:00 |
|
|
Bugra Onal
|
242d90f543
|
Code format fixes
|
2022-08-13 13:58:53 -07:00 |
|
|
Bugra Onal
|
aefe46394c
|
Merge branch 'dev' into multibank
|
2022-08-12 21:45:26 -07:00 |
|
|
Bugra Onal
|
6ba2a9bca7
|
Make sure num_wmasks is 0 when no wmask is generated
|
2022-08-10 16:35:39 -07:00 |
|
|
Bugra Onal
|
f743b1f068
|
Convert to new modules format
|
2022-08-10 16:34:49 -07:00 |
|
|
Bugra Onal
|
2d849aef39
|
Write size updated in recompute_sizes
|
2022-08-10 15:36:41 -07:00 |
|
|
Bugra Onal
|
48fce6485d
|
write_size None initialization fixed
|
2022-08-04 16:37:21 -07:00 |
|
|
Bugra Onal
|
2ed107f9ff
|
Fix the total addr_size
|
2022-08-04 16:36:26 -07:00 |
|
|
Bugra Onal
|
0ca14a3662
|
Fix typo on w_en
|
2022-08-04 16:35:09 -07:00 |
|
|
samuelkcrow
|
1177df6193
|
move most of place_instances to base
|
2022-08-01 10:33:48 -07:00 |
|
|
Bugra Onal
|
7fe0f647ef
|
fix
|
2022-07-28 17:00:16 -07:00 |
|
|
Bugra Onal
|
a361d9f7bb
|
Fixed write_size checks for None
|
2022-07-28 16:45:58 -07:00 |
|
|
Bugra Onal
|
6efe974d7b
|
Delete sram_base form rebase
|
2022-07-28 16:02:39 -07:00 |
|
|
Bugra Onal
|
9771bb7056
|
Don't generate wmask and if word per line is 1
|
2022-07-28 15:59:28 -07:00 |
|
|
Bugra Onal
|
02d8eca640
|
Fix indentation
|
2022-07-28 15:07:19 -07:00 |
|
|
Bugra Onal
|
36e23dc80f
|
Moved template module to new modules folder
|
2022-07-28 15:05:34 -07:00 |
|
|
Bugra Onal
|
3f1a5a2051
|
Shrunk address register in multibank verilog
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
5f45f7db15
|
Fixed the bad commas with post-process regex
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
a75951b5b1
|
write_size init in sram_config
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
898a1f07f5
|
Fixed verilog filename double extension
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
c1e891b2fb
|
Multibank file generation (messy)
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
846dfc79dc
|
modified template engine & sram multibank class
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
30f5638b9f
|
Replaced instances of addr_size with bank_addr
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
29079bd6ac
|
Added conditional sections to template
|
2022-07-28 15:03:41 -07:00 |
|
|
Bugra Onal
|
24bb6f8c11
|
Multibank file generation (messy)
|
2022-07-28 15:03:37 -07:00 |
|
|
samuelkcrow
|
1c8aeaa68a
|
fix imports
|
2022-07-27 11:09:10 -07:00 |
|
|
samuelkcrow
|
2ff9ea4f78
|
move generic functions from control_logic module to new control_logic_base module
|
2022-07-26 23:22:02 -07:00 |
|
|
mrg
|
69d5731d67
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2022-07-22 13:47:19 -07:00 |
|