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OpenRAM/compiler/modules
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Eren Dogan fccdc3c45b Use library imports globally
2022-11-27 13:01:20 -08:00
..
__init__.py
sky130 rba passing :)
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and2_dec.py
Use library imports globally
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and3_dec.py
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and4_dec.py
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2022-11-27 13:01:20 -08:00
bank.py
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bitcell_1port.py
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bitcell_2port.py
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bitcell_array.py
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bitcell_base_array.py
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bitcell_base.py
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col_cap_array.py
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col_cap_bitcell_1port.py
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2022-11-27 13:01:20 -08:00
col_cap_bitcell_2port.py
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2022-11-27 13:01:20 -08:00
column_decoder.py
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2022-11-27 13:01:20 -08:00
column_mux_array.py
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column_mux.py
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2022-11-27 13:01:20 -08:00
control_logic_base.py
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2022-11-27 13:01:20 -08:00
control_logic.py
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2022-11-27 13:01:20 -08:00
delay_chain.py
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2022-11-27 13:01:20 -08:00
dff_array.py
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2022-11-27 13:01:20 -08:00
dff_buf_array.py
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dff_buf.py
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dff_inv_array.py
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dff_inv.py
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dff.py
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2022-11-27 13:01:20 -08:00
dummy_array.py
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2022-11-27 13:01:20 -08:00
dummy_bitcell_1port.py
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2022-11-27 13:01:20 -08:00
dummy_bitcell_2port.py
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2022-11-27 13:01:20 -08:00
dummy_pbitcell.py
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global_bitcell_array.py
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hierarchical_decoder.py
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2022-11-27 13:01:20 -08:00
hierarchical_predecode2x4.py
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hierarchical_predecode3x8.py
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hierarchical_predecode4x16.py
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hierarchical_predecode.py
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2022-11-27 13:01:20 -08:00
internal_base.py
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2022-11-27 13:01:20 -08:00
inv_dec.py
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local_bitcell_array.py
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multibank.py
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nand2_dec.py
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nand3_dec.py
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2022-11-27 13:01:20 -08:00
nand4_dec.py
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2022-11-27 13:01:20 -08:00
orig_bitcell_array.py
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pand2.py
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pand3.py
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pand4.py
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pbitcell.py
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pbuf_dec.py
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pbuf.py
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pdriver.py
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pgate.py
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pinv_dec.py
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pinv.py
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pinvbuf.py
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pnand2.py
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pnand3.py
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pnand4.py
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2022-11-27 13:01:20 -08:00
pnor2.py
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2022-11-27 13:01:20 -08:00
port_address.py
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2022-11-27 13:01:20 -08:00
port_data.py
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2022-11-27 13:01:20 -08:00
precharge_array.py
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2022-11-27 13:01:20 -08:00
precharge.py
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2022-11-27 13:01:20 -08:00
ptristate_inv.py
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ptx.py
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2022-11-27 13:01:20 -08:00
pwrite_driver.py
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2022-11-27 13:01:20 -08:00
replica_bitcell_1port.py
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replica_bitcell_2port.py
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replica_bitcell_array.py
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replica_column.py
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replica_pbitcell.py
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row_cap_array.py
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row_cap_bitcell_1port.py
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row_cap_bitcell_2port.py
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2022-11-27 13:01:20 -08:00
sense_amp_array.py
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sense_amp.py
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2022-11-27 13:01:20 -08:00
sram_1bank.py
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2022-11-27 13:01:20 -08:00
sram_config.py
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2022-11-27 13:01:20 -08:00
sram_multibank_template.v
Shrunk address register in multibank verilog
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sram_multibank.py
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2022-11-27 13:01:20 -08:00
sram.py
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2022-11-27 13:01:20 -08:00
template.py
Code format fixes
2022-08-13 13:58:53 -07:00
tri_gate_array.py
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2022-11-27 13:01:20 -08:00
tri_gate.py
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2022-11-27 13:01:20 -08:00
wordline_buffer_array.py
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2022-11-27 13:01:20 -08:00
wordline_driver_array.py
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2022-11-27 13:01:20 -08:00
wordline_driver.py
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write_driver_array.py
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write_driver.py
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2022-11-27 13:01:20 -08:00
write_mask_and_array.py
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