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OpenRAM
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1,931 Commits 4 Branches 63 Tags 78 MiB
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87 Commits

Author SHA1 Message Date
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Jesse Cirimelli-Low ed901aba5f changed datetime to date 2019-01-28 10:29:27 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Matt Guthaus 94a6cbc28b Remove extra bracket in pin blokc 2019-01-09 13:44:25 -08:00
Matt Guthaus 7e635d02be Remove indices from pins in lib file 2019-01-09 12:00:00 -08:00
Jesse Cirimelli-Low 6acc8c8902 removed print debug statement 2019-01-03 13:41:25 -08:00
Jesse Cirimelli-Low 53b7e46db4 fixed bug where retrieving git id would fail depending on cwd 2019-01-03 12:28:29 -08:00
Jesse Cirimelli-Low c69e5fdb18 added compile time to datasheet 2019-01-02 10:30:03 -08:00
Jesse Cirimelli-Low cc27736a45 moved DRC and LVS error reports to datasheet.info from datasheet.py 2019-01-02 10:14:45 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low 7a20420030 get ORIG_HEAD with pre-commit hook 2018-12-05 13:38:09 -08:00
Jesse Cirimelli-Low 5646660765 added git id to datasheet 2018-12-03 10:53:50 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Jesse Cirimelli-Low d6c0247ff2 added area to datasheet 2018-11-08 21:30:17 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00