mrg
449a4c2660
Exclude bitcells in other local areas not of interest
2020-09-29 12:15:42 -07:00
mrg
d7e2340e62
Lots of PEP8 cleanup. Refactor path graph to simulation class.
2020-09-29 10:26:31 -07:00
mrg
88731ccd8e
Fix rounding error for wmask with various word_size
2020-09-28 09:53:01 -07:00
Hunter Nichols
af22e438f1
Added option to output an extended configuration file that includes defaults.
2020-09-08 18:40:39 -07:00
Hunter Nichols
73b2277daa
Removed dead code related to older characterization scheme
2020-08-27 17:30:58 -07:00
mrg
652f160aca
Merge branch 'wlbuffer' into dev
2020-08-25 15:50:08 -07:00
mrg
bd8bf9afd8
Remove RBL label at top level of SRAM
2020-08-25 14:42:21 -07:00
mrg
28bd93bf51
Still working on array refactor
2020-08-25 11:50:44 -07:00
jcirimel
9cecf367ee
Merge branch 'dev' into pex
2020-08-17 17:49:41 -07:00
jcirimel
714b57d48e
Merge branch 'dev' into pex
2020-08-17 17:48:21 -07:00
mrg
60224b105f
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2020-08-17 14:20:34 -07:00
mrg
50525e70f4
Fix up to SRAM level with new replica bitcell array ports.
2020-08-13 14:29:10 -07:00
mrg
0bec6f0439
Fix SRAM to use simulation spice instead of LVS spice
2020-08-12 10:41:21 -07:00
jcirimel
02e65a00ef
update pex to work with dev changes
2020-08-03 17:14:34 -07:00
Bob Vanhoof
9b8ef5ef57
fix: generated pex file was not passed correctly to lib characterizer
2020-08-03 10:16:12 +02:00
mrg
487027a9f2
Fix pex file names
2020-07-30 11:35:13 -07:00
Matt Guthaus
68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
...
calibrepex: file copy fix
2020-07-30 08:40:35 -07:00
mrg
f23d2e36a7
Don't obstruct control logic signals with dffs when no column mux.
2020-07-29 10:31:18 -07:00
jcirimel
df4a231c04
fix merge conflicts
2020-07-21 11:38:34 -07:00
mrg
58846a4a25
Limit wordline driver size. Place row addr dff near predecoders.
2020-07-20 17:57:38 -07:00
mrg
0ed81aa923
Removed extraneous shift from added mirroring
2020-07-20 14:11:52 -07:00
mrg
82bbacdfb5
Add data bus gap to dynamically computed channel width
2020-07-20 13:43:57 -07:00
mrg
a36e89e103
Replace data flops depending on channel width
2020-07-20 13:26:05 -07:00
mrg
f35848e4f8
Route col flops separately. Flip port 1 col flop for easier routing.
2020-07-20 12:02:59 -07:00
mrg
ba3d32fa0c
Starting to implement minimizing channel router (not done)
2020-07-16 13:21:44 -07:00
Bob Vanhoof
ee3da91232
calibrepex: file copy fix
2020-07-15 11:50:21 +02:00
mrg
bb8157b3b7
Exit on DRC not run, check for LVSDRC before running in sram_base.
2020-07-14 08:38:49 -07:00
mrg
2011974e01
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
mrg
a3195c0827
Add words_per_row and others in config file.
2020-07-13 12:37:56 -07:00
mrg
282f944b2f
Also write .lvs file since it can be different the .sp
2020-07-03 06:55:35 -07:00
mrg
d48f483248
Fix swapped instance bug in perimeter pins.
2020-07-01 15:10:20 -07:00
mrg
c340870ba0
Channel route dout wires as well in read write ports
2020-07-01 14:44:01 -07:00
mrg
3d0f29ff3a
Fix missing via LVS issues. LVS passing for some 20 tests.
2020-07-01 09:22:59 -07:00
mrg
5626fd182e
Extra track in data bus. Remove old code.
2020-06-30 10:58:24 -07:00
mrg
5f3a45b91b
Compute bus size separately for ports
2020-06-29 05:54:30 -07:00
mrg
751eab202b
Move row addr flops away from predecode. Route spare wen separately on lower layer.
2020-06-28 15:06:29 -07:00
mrg
4df02dad67
Move spare wen_dff to the right by spare columns
2020-06-28 14:28:43 -07:00
mrg
0c9f52e22f
Realign col decoder and control by 1/4 so metal can pass over
2020-06-28 07:15:06 -07:00
mrg
66ea559209
Use channel for dffs all at once
2020-06-27 08:23:12 -07:00
mrg
7220b23402
Add riscv unit tests
2020-06-25 15:34:18 -07:00
mrg
52ee7b0a19
Disable perimeter pins and make an option
2020-06-14 16:44:10 -07:00
mrg
78be9f367a
Add brain-dead router pins to perimeter
2020-06-14 15:52:09 -07:00
mrg
8e8a97cc4b
Add correct boundary to SRAM
2020-06-14 14:17:35 -07:00
Aditi Sinha
d5041afebc
Merge branch 'dev' into bisr
2020-06-07 16:27:25 +00:00
mrg
717188f85c
Change L shape of rbl route
2020-06-04 11:03:39 -07:00
Aditi Sinha
eb0c595dbe
SRAM layout and functional tests with spare cols
2020-06-03 12:31:30 +00:00
Aditi Sinha
c7d86b21ae
Spare cols with wmask enabled
2020-05-16 10:09:03 +00:00
Aditi Sinha
8bd1052fc2
Spare columns in full sram layout
2020-05-14 10:30:29 +00:00
Aditi Sinha
a5c211bd90
Merge branch 'dev' into bisr
2020-05-13 22:39:29 +00:00
mrg
b7c66d7e07
Changes to simplify metal preferred directions and pitches.
...
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
mrg
Hunter Nichols
jcirimel
Bob Vanhoof
Aditi Sinha