mrg c340870ba0 Channel route dout wires as well in read write ports

2020-07-01 14:44:01 -07:00

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sram_1bank.py

Channel route dout wires as well in read write ports

2020-07-01 14:44:01 -07:00

sram_2bank.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

sram_base.py

Add correct boundary to SRAM

2020-06-14 14:17:35 -07:00

sram_config.py

changes to support spare columns

2020-04-14 03:09:10 +00:00

sram.py

Fix lvs_write in sram class

2020-04-06 15:20:59 -07:00