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OpenRAM
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196 Commits

Author SHA1 Message Date
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
David Ratchkov 123cc371be - Fix disabled power char 2020-04-17 16:09:58 -07:00
David Ratchkov 1f816e2823 - Characterize actual disabled power (read mode only) 
- Report rise/fall power individually
 2020-04-17 14:55:17 -07:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
Hunter Nichols e4fef73e3f Fixed issues with bitcell measurements variable names, made target write ports required during characterization 2020-02-19 15:34:31 -08:00
Hunter Nichols 843fce41d7 Fixed issues with sen control logic for read ports. 2020-02-19 03:06:11 -08:00
Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell 2020-01-27 11:50:43 +00:00
jcirimel 40c01dab85 fix bl in stim file 2020-01-21 01:44:15 -08:00
jcirimel 73691f6054 fix bug in top level bitline label placement 2020-01-21 00:20:52 -08:00
jcirimel 364842569a fix s_en in stim 2020-01-16 12:16:49 -08:00
jcirimel 075bf0d841 label bitcell in stim, add s_en top level to stim 2020-01-16 03:51:29 -08:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
Matt Guthaus c09005dab9 Redo logic for detecting bad bitlines 2019-08-10 17:32:36 -07:00
Hunter Nichols 1d22d39667 Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Hunter Nichols 6860d3258e Added graph functions to compute analytical delay based on graph path. 2019-08-07 01:50:48 -07:00
Matt Guthaus aae8566ff2 Update golden delays. Fix uninitialized boolean. 2019-08-05 15:45:59 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00
Hunter Nichols c12dd987dc Fixed pbitcell graph edge formation. 2019-07-30 00:49:43 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 3327fa58c0 Add some signal names to functional test comments 2019-07-26 14:49:53 -07:00
Matt Guthaus 8ebc568e8b Minor cleanup. Skip more tests until analytical fixed. 2019-07-26 08:33:06 -07:00
Matt Guthaus 54b312eaf9 Add return type 2019-07-24 17:00:38 -07:00
Matt Guthaus 2f03c594c5 Remove success initialization 2019-07-24 16:59:19 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
Matt Guthaus fe0db68965 Refactor to share get_measurement_variant 2019-07-24 11:29:29 -07:00