 Hunter Nichols
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84ba5c55d1
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Merged with dev
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2020-11-10 15:47:56 -08:00 |
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 mrg
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57e708a6e1
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
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10542d6cc3
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Output DRC and LVS run files to output directory.
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2020-11-09 11:12:31 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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Hunter Nichols
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12a8531248
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Allowed for OPTS writeback of words_per_row if automatically generated during generation.
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2020-10-21 03:02:39 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
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b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
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2020-10-01 11:10:18 -07:00 |
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mrg
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18c8ad265e
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Unique name for sram channel routes
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2020-10-01 09:55:34 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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Hunter Nichols
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af22e438f1
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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652f160aca
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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mrg
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bd8bf9afd8
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Remove RBL label at top level of SRAM
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2020-08-25 14:42:21 -07:00 |
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mrg
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28bd93bf51
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Still working on array refactor
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2020-08-25 11:50:44 -07:00 |
|
 jcirimel
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9cecf367ee
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Merge branch 'dev' into pex
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2020-08-17 17:49:41 -07:00 |
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jcirimel
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714b57d48e
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Merge branch 'dev' into pex
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2020-08-17 17:48:21 -07:00 |
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mrg
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60224b105f
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-17 14:20:34 -07:00 |
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mrg
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50525e70f4
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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mrg
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0bec6f0439
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Fix SRAM to use simulation spice instead of LVS spice
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2020-08-12 10:41:21 -07:00 |
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jcirimel
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02e65a00ef
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update pex to work with dev changes
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2020-08-03 17:14:34 -07:00 |
|
 Bob Vanhoof
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9b8ef5ef57
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fix: generated pex file was not passed correctly to lib characterizer
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2020-08-03 10:16:12 +02:00 |
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mrg
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487027a9f2
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Fix pex file names
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2020-07-30 11:35:13 -07:00 |
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Matt Guthaus
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68387ec525
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Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
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2020-07-30 08:40:35 -07:00 |
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mrg
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f23d2e36a7
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Don't obstruct control logic signals with dffs when no column mux.
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2020-07-29 10:31:18 -07:00 |
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jcirimel
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df4a231c04
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fix merge conflicts
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2020-07-21 11:38:34 -07:00 |
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mrg
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58846a4a25
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Limit wordline driver size. Place row addr dff near predecoders.
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2020-07-20 17:57:38 -07:00 |
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mrg
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0ed81aa923
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Removed extraneous shift from added mirroring
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2020-07-20 14:11:52 -07:00 |
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mrg
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82bbacdfb5
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Add data bus gap to dynamically computed channel width
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2020-07-20 13:43:57 -07:00 |
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mrg
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a36e89e103
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Replace data flops depending on channel width
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2020-07-20 13:26:05 -07:00 |
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mrg
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f35848e4f8
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Route col flops separately. Flip port 1 col flop for easier routing.
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2020-07-20 12:02:59 -07:00 |
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mrg
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ba3d32fa0c
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Starting to implement minimizing channel router (not done)
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2020-07-16 13:21:44 -07:00 |
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Bob Vanhoof
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ee3da91232
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calibrepex: file copy fix
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2020-07-15 11:50:21 +02:00 |
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mrg
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bb8157b3b7
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Exit on DRC not run, check for LVSDRC before running in sram_base.
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2020-07-14 08:38:49 -07:00 |
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mrg
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2011974e01
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Make drc and lvs errors a member variable. Run only once.
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2020-07-13 12:49:24 -07:00 |
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mrg
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a3195c0827
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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mrg
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282f944b2f
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Also write .lvs file since it can be different the .sp
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2020-07-03 06:55:35 -07:00 |
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mrg
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d48f483248
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Fix swapped instance bug in perimeter pins.
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2020-07-01 15:10:20 -07:00 |
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mrg
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c340870ba0
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Channel route dout wires as well in read write ports
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2020-07-01 14:44:01 -07:00 |
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mrg
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3d0f29ff3a
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Fix missing via LVS issues. LVS passing for some 20 tests.
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2020-07-01 09:22:59 -07:00 |
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mrg
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5626fd182e
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Extra track in data bus. Remove old code.
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2020-06-30 10:58:24 -07:00 |
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mrg
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5f3a45b91b
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Compute bus size separately for ports
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2020-06-29 05:54:30 -07:00 |
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mrg
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751eab202b
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Move row addr flops away from predecode. Route spare wen separately on lower layer.
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2020-06-28 15:06:29 -07:00 |
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