luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,874 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3874 Commits

Author SHA1 Message Date
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg fdf51c5a00 Add port option to precharge array 2020-06-02 11:44:22 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg 45b0601e4b Fix via directions in s8 col mux 2020-06-02 11:43:31 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg 620604603c Fixed offset jogs 2020-06-02 10:08:37 -07:00
mrg e69b665689 Flatten pbitcell_1 too 2020-06-02 09:31:43 -07:00
mrg b0aa70ffda Fix precharge vdd route layer 2020-06-02 09:23:27 -07:00
Joey Kunzler b39579c109 temp drc fix for regression tests 2020-06-01 20:55:15 -07:00
mrg 9ecf98a4c3 SRAM factory uses default name for first instance even if it has arguments. 2020-06-01 16:46:22 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
Joey Kunzler b00163e4e1 lvs fix for regression tests 2020-05-29 13:50:34 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
jcirimel 575278998d write only used bitcells to top level in stim and pex output 2020-05-28 23:56:15 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha c14190c5aa Changes in control logic for spare columns 2020-05-14 10:41:54 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
mrg a305d788d7 Vertical gates need both well contacts. 2020-05-13 16:54:35 -07:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg f8bcc54338 Determine width after routing with no well contacts. 2020-05-13 16:04:38 -07:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg 848241a3ad PEP8 cleanup 2020-05-11 16:22:17 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Aditi Sinha 5c50cf234b Fixed lvs errors for spare columns 2020-05-09 07:56:19 +00:00
jcirimel 5666e79287 Merge branch 'dev' into discrete_models 2020-05-08 03:13:16 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
jcirimel d8a51ecafb remove prints, scaling bug fix 2020-05-05 21:59:28 -07:00
jcirimel 71a1dd8f38 fix tx binning in col mux for memories with >1 word per row 2020-05-05 16:35:51 -07:00
Joey Kunzler 91dbbed9ba added horizontal trunk route edit to vertical trunk route 2020-05-05 12:18:26 -07:00
jcirimel 0f9e38881c update stim for large pex layouts 2020-05-04 03:05:33 -07:00
jcirimel 89688f8ea9 fix pex for larger memories 2020-05-04 01:31:51 -07:00
Aditi Sinha e30938fb66 Spare columns working at bank level 2020-05-03 15:23:30 +00:00
Aditi Sinha 49918b0716 New lib syntax for golden results 2020-05-02 09:44:56 +00:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00