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OpenRAM
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4273 Commits

Author SHA1 Message Date
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 82a5fbd4d4 Set theme jekyll-theme-dinky 2018-11-16 08:56:44 -08:00
Matt Guthaus a1526c0394 Set theme jekyll-theme-midnight 2018-11-16 08:54:45 -08:00
Matt Guthaus 935cc5109b Set theme jekyll-theme-hacker 2018-11-16 08:37:54 -08:00
Matt Guthaus ee9aad1b21 Errors in contributors. 2018-11-16 08:26:09 -08:00
Matt Guthaus 26814f92ef Clarify basic setup instructions. 2018-11-16 08:25:04 -08:00
Matt Guthaus 63038480fc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-16 08:23:54 -08:00
Matt Guthaus ff67e772fa Fix extra escape in README 2018-11-15 17:28:06 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 43472dfa46 Modify sense amp to cross coupled inverter 2018-11-15 16:55:18 -08:00
Matt Guthaus 65d341619c Fix typos in README 2018-11-15 15:48:15 -08:00
Matt Guthaus efb0cf25bf Update link to commits for each branch 2018-11-15 15:35:00 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Matt Guthaus 347a68074c Merge remote-tracking branch 'origin/dev' into multiport_layout 2018-11-15 15:25:34 -08:00
Matt Guthaus e0c679054d Add new README.md with badges. 2018-11-15 15:15:37 -08:00
Matt Guthaus c3670fc91d Add new README.md with badges. 2018-11-15 15:09:38 -08:00
Matt Guthaus 5cd89fd7da Add image and further README details 2018-11-15 14:54:56 -08:00
Matt Guthaus 61eb281038 More README.md updates 2018-11-15 14:38:28 -08:00
Matt Guthaus 7b53dffbc6 Plural error 2018-11-15 14:29:32 -08:00
Matt Guthaus 43a7c2e334 Add more information to README.md file 2018-11-15 14:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Matt Guthaus f87c72fe77 Merge branch 'dev' into multiport_layout 2018-11-15 12:59:15 -08:00
Matt Guthaus a74baccef2 Convert link to relative commits 2018-11-15 12:49:10 -08:00
Matt Guthaus 89e5ce8a95 Convert link to relative commits 2018-11-15 12:47:47 -08:00
Matt Guthaus d3803d8c81 Convert link to relative commits 2018-11-15 12:46:19 -08:00
Matt Guthaus 7819844269 Remove broken artifact link 2018-11-15 12:42:13 -08:00
Matt Guthaus cccd815817 Add read-only guest token for pipeline badge access 2018-11-15 12:14:35 -08:00
Matt Guthaus 487e61457b Some small updates to README.md 2018-11-15 11:33:15 -08:00
Matt Guthaus 890d93d776 Update image paths. Add download badge. 2018-11-15 11:20:40 -08:00
Matt Guthaus f3a1acb617 Rename badge file 2018-11-15 11:08:36 -08:00
Matt Guthaus 6e40e2b9c7 Add initial README.md features with badges and links. 2018-11-15 11:07:04 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Hunter Nichols e9f6566e59 Fixed merge conflict, moved control logic mod instantiation, removed some commented out code. 2018-11-14 13:53:27 -08:00
Hunter Nichols 05773ad16e Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45 2018-11-14 11:53:13 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Hunter Nichols 80bc5b49c1 Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell. 2018-11-14 11:00:37 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. 2018-11-13 22:24:18 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse 2018-11-13 17:29:43 -08:00