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README.md
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README.md
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# BASIC SETUP
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# OpenRAM
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Master: [](https://github.com/VLSIDA/OpenRAM/commits)
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Dev: [](https://github.com/VLSIDA/OpenRAM/commits)
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[](https://github.com/VLSIDA/OpenRAM/archive/master.zip)
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[](./LICENSE)
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Please look at the OpenRAM ICCAD paper and presentation in the repository:
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https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_paper.pdf
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https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_presentation.pdf
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An open-source static random access memory (SRAM) compiler.
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# What is OpenRAM?
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<img align="right" width="25%" src="images/SCMOS_16kb_sram.jpg">
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OpenRAM is an open-source Python framework to create the layout,
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netlists, timing and power models, placement and routing models, and
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other views necessary to use SRAMs in ASIC design. OpenRAM supports
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integration in both commercial and open-source flows with both
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predictive and fabricable technologies.
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# Basic Setup
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The OpenRAM compiler has very few dependencies:
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* ngspice-26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
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* Python 2.7 and higher (currently excludes Python 3 and up)
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* Python numpy
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* a setup script for each technology
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* a technology directory for each technology with the base cells
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+ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
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+ Python 3.5 or higher
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+ Python numpy (pip3 install numpy to install)
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+ flask_table (pip3 install flask to install)
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If you want to perform DRC and LVS, you will need either:
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* Calibre (for FreePDK45 or SCMOS)
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* Magic + Netgen (for SCMOS only)
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+ Calibre (for [FreePDK45])
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+ [Magic] + [Netgen] (for [SCMOS])
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You must set two environment variables:
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+ OPENRAM\_HOME should point to the compiler source directory.
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+ OPENERAM\_TECH should point to a root technology directory.
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For example add this to your .bashrc:
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You must set two environment variables: OPENRAM_HOME should point to
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the compiler source directory. OPENERAM_TECH should point to a root
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technology directory that contains subdirs of all other technologies.
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For example, in bash, add to your .bashrc:
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```
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export OPENRAM_HOME="$HOME/OpenRAM/compiler"
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export OPENRAM_TECH="$HOME/OpenRAM/technology"
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export OPENRAM_HOME="$HOME/openram/compiler"
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export OPENRAM_TECH="$HOME/openram/technology"
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```
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For example, in csh/tcsh, add to your .cshrc/.tcshrc:
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```
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setenv OPENRAM_HOME "$HOME/OpenRAM/compiler"
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setenv OPENRAM_TECH "$HOME/OpenRAM/technology"
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```
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If you are using FreePDK, you should also have that set up and have the
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environment variable point to the PDK.
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For example, in bash, add to your .bashrc:
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We include the tech files necessary for [FreePDK45] and [SCMOS]
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SCN4M_SUBM. The [SCMOS] spice models, however, are generic and should
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be replaced with foundry models. If you are using [FreePDK45], you
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should also have that set up and have the environment variable point
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to the PDK. For example add this to your .bashrc:
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```
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export FREEPDK45="/bsoe/software/design-kits/FreePDK45"
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```
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For example, in csh/tcsh, add to your .tcshrc:
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You may get the entire [FreePDK45 PDK here][FreePDK45].
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If you are using [SCMOS], you should install [Magic] and [Netgen].
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We have included the most recent SCN4M_SUBM design rules from [Qflow].
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# Basic Usage
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Once you have defined the environment, you can run OpenRAM from the command line
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using a single configuration file written in Python. You may wish to add
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$OPENRAM\_HOME to your $PYTHONPATH.
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For example, create a file called *myconfig.py* specifying the following
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parameters for your memory:
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```
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setenv FREEPDK45 "/bsoe/software/design-kits/FreePDK45"
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# Data word size
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word_size = 2
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# Number of words in the memory
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num_words = 16
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# Technology to use in $OPENRAM\_TECH
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tech_name = "scn4m_subm"
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# Process corners to characterize
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process_corners = ["TT"]
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# Voltage corners to characterize
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supply_voltages = [ 3.3 ]
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# Temperature corners to characterize
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temperatures = [ 25 ]
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# Output directory for the results
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output_path = "temp"
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# Output file base name
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output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
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# Disable analytical models for full characterization (WARNING: slow!)
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# analytical_delay = False
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```
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We do not distribute the PDK, but you may get it from:
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https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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If you are using SCMOS, you should install Magic and netgen from:
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http://opencircuitdesign.com/magic/
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http://opencircuitdesign.com/netgen/
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In addition, you will need to install the MOSIS SCMOS rules for scn3me_subm
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that are part of QFlow:
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http://opencircuitdesign.com/qflow/
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# DIRECTORY STRUCTURE
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* compiler - openram compiler itself (pointed to by OPENRAM_HOME)
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* compiler/characterizer - timing characterization code
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* compiler/gdsMill - GDSII reader/writer
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* compiler/router - detailed router
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* compiler/tests - unit tests
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* technology - openram technology directory (pointed to by OPENRAM_TECH)
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* technology/freepdk45 - example configuration library for freepdk45 technology node
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* technology/scn3me_subm - example configuration library SCMOS technology node
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* technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies
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You can then run OpenRAM by executing:
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```
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python3 $OPENRAM\_HOME/openram.py myconfig
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```
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You can see all of the options for the configuration file in
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$OPENRAM\_HOME/options.py
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# UNIT TESTS
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# Unit Tests
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Regression testing performs a number of tests for all modules in OpenRAM.
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From the unit test directory ($OPENRAM\_HOME/tests),
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use the following command to run all regression tests:
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Use the command:
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```
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python regress.py
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python3 regress.py
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```
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To run a specific test:
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```
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python {unit test}.py
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python3 {unit test}.py
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```
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The unit tests take the same arguments as openram.py itself.
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To increase the verbosity of the test, add one (or more) -v options:
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```
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python tests/00_code_format_check_test.py -v -t freepdk45
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python3 tests/00_code_format_check_test.py -v -t freepdk45
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```
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To specify a particular technology use "-t <techname>" such as
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"-t scn3me_subm". The default for a unit test is freepdk45 whereas
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the default for openram.py is specified in the configuration file.
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"-t freepdk45" or "-t scn4m\_subm". The default for a unit test is scn4m_subm.
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The default for openram.py is specified in the configuration file.
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A regression daemon script that can be used with cron is included in
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a separate repository at https://github.com/mguthaus/openram-daemons
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```
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regress_daemon.py
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regress_daemon.sh
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```
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This updates a git repository, checks out code, and sends an email
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report with status information.
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# CREATING CUSTOM TECHNOLOGIES
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# Porting to a New Technology
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All setup scripts should be in the setup_scripts directory under the
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$OPENRAM_TECH directory. Please look at the following file for an
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If you want to support a enw technology, you will need to create:
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+ a setup script for each technology you want to use
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+ a technology directory for each technology with the base cells
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All setup scripts should be in the setup\_scripts directory under the
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$OPENRAM\_TECH directory. We provide two technology examples for
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[SCMOS] and [FreePDK45]. Please look at the following file for an
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example of what is needed for OpenRAM:
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```
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$OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py
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```
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Each setup script should be named as: setup_openram_{tech name}.py.
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Each specific technology (e.g., freepdk45) should be a subdirectory
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Each setup script should be named as: setup\_openram\_{tech name}.py.
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Each specific technology (e.g., [FreePDK45]) should be a subdirectory
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(e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:
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1. gds_lib folder with all the .gds (premade) library cells. At a
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minimum this includes:
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* ms_flop.gds
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* sense_amp.gds
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* write_driver.gds
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* cell_6t.gds
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* replica_cell_6t.gds
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* tri_gate.gds
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2. sp_lib folder with all the .sp (premade) library netlists for the above cells.
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3. layers.map
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4. A valid tech Python module (tech directory with __init__.py and tech.py) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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* Layer information
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* etc.
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* gds_lib folder with all the .gds (premade) library cells:
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* dff.gds
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* sense_amp.gds
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* write_driver.gds
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* cell_6t.gds
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* replica\_cell\_6t.gds
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* sp_lib folder with all the .sp (premade) library netlists for the above cells.
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* layers.map
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* A valid tech Python module (tech directory with __init__.py and tech.py) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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* Layer information
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* Spice and supply information
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* etc.
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# DEBUGGING
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# Get Involved
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When OpenRAM runs, it puts files in a temporary directory that is
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shown in the banner at the top. Like:
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```
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/tmp/openram_mrg_18128_temp/
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```
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This is where simulations and DRC/LVS get run so there is no network
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traffic. The directory name is unique for each person and run of
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OpenRAM to not clobber any files and allow simultaneous runs. If it
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passes, the files are deleted. If it fails, you will see these files:
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* temp.gds is the layout
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* (.mag files if using SCMOS)
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* temp.sp is the netlist
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* test1.drc.err is the std err output of the DRC command
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* test1.drc.out is the standard output of the DRC command
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* test1.drc.results is the DRC results file
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* test1.lvs.err is the std err output of the LVS command
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* test1.lvs.out is the standard output of the LVS command
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* test1.lvs.results is the DRC results file
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+ Report bugs by submitting [Github issues].
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+ Develop new features (see [how to contribute](./CONTRIBUTING.md))
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+ Submit code/fixes using a [Github pull request]
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+ Follow our [project][Github projects].
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+ Read and cite our [ICCAD paper][OpenRAMpaper]
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Depending on your DRC/LVS tools, there will also be:
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* _calibreDRC.rul_ is the DRC rule file (Calibre)
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* dc_runset is the command file (Calibre)
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* extracted.sp (Calibre)
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* run_lvs.sh is a Netgen script for LVS (Netgen)
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* run_drc.sh is a Magic script for DRC (Magic)
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* <topcell>.spice (Magic)
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# Further Help
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If DRC/LVS fails, the first thing is to check if it ran in the .out and
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.err file. This shows the standard output and error output from
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running DRC/LVS. If there is a setup problem it will be shown here.
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+ [Additional hints](./HINTS.md)
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+ [OpenRAM Slack Workspace][Slack]
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+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
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+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
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If DRC/LVS runs, but doesn't pass, you then should look at the .results
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file. If the DRC fails, it will typically show you the command that was used
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to run Calibre or Magic+Netgen.
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# License
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To debug, you will need a layout viewer. I prefer to use Glade
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on my Mac, but you can also use Calibre, Magic, etc.
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OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
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1. Calibre
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# Contributors & Acknowledgment
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Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file:
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```
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calibredrv temp.gds
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```
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Select Verification->Start RVE and select the results database file in
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the new form (e.g., test1.drc.db). This will start the RVE (results
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viewer). Scroll through the check pane and find the DRC check with an
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error. Select it and it will open some numbers to the right. Double
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click on any of the errors in the result browser. These will be
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labelled as numbers "1 2 3 4" for example will be 4 DRC errors.
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- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
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- [James Stine] from [VLSIARCH] co-founded the project.
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- Hunter Nichols maintains and updates the timing characterization.
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- Michael Grims created and maintains the multiport netlist code.
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- Jennifer Sowash is creating the OpenRAM IP library.
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- Jesse Cirimelli-Low created the datasheet generation.
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- Samira Ataei created early multi-bank layouts and control logic.
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- Bin Wu created early parameterized cells.
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- Yusu Wang is porting parameterized cells to new technologies.
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- Brian Chen created early prototypes of the timing characterizer.
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- Jeff Butera created early prototypes of the bank layout.
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In the viewer ">" opens the layout down a level.
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* * *
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2. Glade
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[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
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[James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
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[VLSIDA]: https://vlsida.soe.ucsc.edu
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[VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
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[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
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You can view errors in Glade as well. I like this because it is on my laptop.
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You can get it from: http://www.peardrop.co.uk/glade/
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[Github issues]: https://github.com/OpenRAM/OpenRAM/issues
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[Github pull request]: https://github.com/OpenRAM/OpenRAM/pulls
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[Github projects]: https://github.com/OpenRAM/OpenRAM/projects
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To remote display over X windows, you need to disable OpenGL acceleration or use vnc
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or something. You can disable by adding this to your .bashrc in bash:
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```
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export GLADE_USE_OPENGL=no
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```
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or in .cshrc/.tcshrc in csh/tcsh:
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```
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setenv GLADE_USE_OPENGAL no
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```
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To use this with the FreePDK45 or SCMOS layer views you should use the
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tech files. Then create a .glade.py file in your user directory with
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these commands to load the technology layers:
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```
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ui().importCds("default",
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"/Users/mrg/techfiles/freepdk45/display.drf",
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"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1,
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"/Users/mrg/techfiles/freepdk45/layers.map")
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```
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Obviously, edit the paths to point to your directory. To switch
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between processes, you have to change the importCds command (or you
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can manually run the command each time you start glade).
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[email me]: mailto:mrg+openram@ucsc.edu
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[dev-group]: mailto:openram-dev-group@ucsc.edu
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[user-group]: mailto:openram-user-group@ucsc.edu
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[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu
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[user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu
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To load the errors, you simply do Verify->Import Calibre Errors select
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the .results file from Calibre.
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[Magic]: http://opencircuitdesign.com/magic/
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[Netgen]: http://opencircuitdesign.com/netgen/
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[Qflow]: http://opencircuitdesign.com/qflow/history.html
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[Ngspice]: http://ngspice.sourceforge.net/
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3. Magic
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Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules
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and Magic from: http://opencircuitdesign.com/
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When running DRC or extraction, OpenRAM will load the GDS file, save
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the .ext/.mag files, and export an extracted netlist (.spice).
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4. It is possible to use other viewers as well, such as:
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* LayoutEditor http://www.layouteditor.net/
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# Example to output/input .gds layout files from/to Cadence
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1. To create your component layouts, you should stream them to
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individual gds files using our provided layermap and flatten
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cells. For example,
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```
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strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds
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```
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2. To stream a layout back into Cadence, do this:
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```
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strmin -layerMap layers.map -attachTechFileOfLib NCSU_TechLib_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds
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```
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When you import a gds file, make sure to attach the correct tech lib
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or you will get incorrect layers in the resulting library.
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[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/
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[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
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[Slack]: https://join.slack.com/t/openram/shared_invite/enQtNDgxMjc3NzU5NTI1LTE4ODMyM2I0Mzk2ZmFiMjgwYTYyMTQ4NTgwMmUwMDhiM2E1MDViNDRjYzU1NjJhZTQxNWZjMzE3M2FlODBmZjA
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<?xml version="1.0" encoding="utf-8"?>
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<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="112" height="20"><linearGradient id="b" x2="0" y2="100%"><stop offset="0" stop-color="#bbb" stop-opacity=".1"/><stop offset="1" stop-opacity=".1"/></linearGradient><clipPath id="a"><rect width="112" height="20" rx="3" fill="#fff"/></clipPath><g clip-path="url(#a)"><path fill="#555" d="M0 0h71v20H0z"/><path fill="#007ec6" d="M71 0h41v20H71z"/><path fill="url(#b)" d="M0 0h112v20H0z"/></g><g fill="#fff" text-anchor="middle" font-family="DejaVu Sans,Verdana,Geneva,sans-serif" font-size="110"><text x="365" y="150" fill="#010101" fill-opacity=".3" transform="scale(.1)" textLength="610">download </text><text x="365" y="140" transform="scale(.1)" textLength="610">download </text><text x="905" y="150" fill="#010101" fill-opacity=".3" transform="scale(.1)" textLength="310">latest</text><text x="905" y="140" transform="scale(.1)" textLength="310">latest</text></g> </svg>
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After Width: | Height: | Size: 1004 B |
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@ -0,0 +1 @@
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<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="136" height="20"><linearGradient id="b" x2="0" y2="100%"><stop offset="0" stop-color="#bbb" stop-opacity=".1"/><stop offset="1" stop-opacity=".1"/></linearGradient><clipPath id="a"><rect width="136" height="20" rx="3" fill="#fff"/></clipPath><g clip-path="url(#a)"><path fill="#555" d="M0 0h51v20H0z"/><path fill="#007ec6" d="M51 0h85v20H51z"/><path fill="url(#b)" d="M0 0h136v20H0z"/></g><g fill="#fff" text-anchor="middle" font-family="DejaVu Sans,Verdana,Geneva,sans-serif" font-size="110"> <text x="265" y="150" fill="#010101" fill-opacity=".3" transform="scale(.1)" textLength="410">License</text><text x="265" y="140" transform="scale(.1)" textLength="410">License</text><text x="925" y="150" fill="#010101" fill-opacity=".3" transform="scale(.1)" textLength="750">BSD 3-Clause</text><text x="925" y="140" transform="scale(.1)" textLength="750">BSD 3-Clause</text></g> </svg>
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After Width: | Height: | Size: 971 B |
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Reference in New Issue