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Matt Guthaus
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README.md
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README.md
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An open-source static random access memory (SRAM) compiler.
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# Why OpenRAM?
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# What is OpenRAM?
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OpenRAM is an open-source Python framework to create the layout,
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netlists, timing and power models, placement and routing models, and
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other views necessary to use SRAMs in ASIC design. OpenRAM supports
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integration in both commercial and open-source flows with both
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predictive and fabricable technologies.
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# Basic Setup
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@ -52,6 +57,34 @@ We do not distribute the PDK, but you may download [FreePDK45]
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If you are using [SCMOS], you should install [Magic] and [Netgen].
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We have included the SCN4M design rules from [Qflow].
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# Basic Usage
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Once you have defined the environment, you can run OpenRAM from the command line
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using a single configuration file written in Python. For example,
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create a file called myconfig.py specifying the following parameters:
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```
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word_size = 2
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num_words = 16
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tech_name = "scn4m_subm"
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process_corners = ["TT"]
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supply_voltages = [ 3.3 ]
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temperatures = [ 25 ]
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output_path = "temp"
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output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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```
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and run OpenRAM by executing:
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```
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$OPENRAM\_HOME/openram.py myconfig
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```
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You can see all of the options for the configuration file in
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$OPENRAM\_HOME/options.py
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# Directory Structure
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* compiler - openram compiler itself (pointed to by OPENRAM_HOME)
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@ -76,8 +109,8 @@ We have included the SCN4M design rules from [Qflow].
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# Unit Tests
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Regression testing performs a number of tests for all modules in OpenRAM.
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Use the command:
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From the unit test directory ($OPENRAM\_HOME/tests),
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use the following command to run all regression tests:
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```
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python3 regress.py
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```
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@ -112,21 +145,20 @@ Each setup script should be named as: setup\_openram\_{tech name}.py.
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Each specific technology (e.g., [FreePDK45]) should be a subdirectory
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(e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:
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1. gds_lib folder with all the .gds (premade) library cells. At a
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minimum this includes:
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* ms_flop.gds
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* sense_amp.gds
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* write_driver.gds
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* cell_6t.gds
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* replica_cell_6t.gds
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* tri_gate.gds
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2. sp_lib folder with all the .sp (premade) library netlists for the above cells.
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3. layers.map
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4. A valid tech Python module (tech directory with __init__.py and tech.py) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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* Layer information
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* etc.
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* gds_lib folder with all the .gds (premade) library cells:
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* dff.gds
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* sense_amp.gds
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* write_driver.gds
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* cell_6t.gds
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* replica\_cell\_6t.gds
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* sp_lib folder with all the .sp (premade) library netlists for the above cells.
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* layers.map
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* A valid tech Python module (tech directory with __init__.py and tech.py) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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* Layer information
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* Spice and supply information
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* etc.
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# Get Involved
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@ -142,22 +174,36 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
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# Contributors & Acknowledgment
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- [Matthew Guthaus][Matthew Guthaus] created the OpenRAM project and is the lead architect.
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- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
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- [James Stine] from [VLSIARCH] co-founded the project.
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- Hunter Nichols maintains and updates the timing characterization.
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- Michael Grims created and maintains the multiport netlist code.
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- Jennifer Sowash is creating the OpenRAM IP library.
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- Jesse Cirimelli-Low created the datasheet generation.
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- Samira Ataei created early multi-bank layouts.
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- Bin Wu created early parameterized cells.
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- Yusu Wang is porting parameterized cells to new technologies.
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- Brian Chen created early prototypes of the timing characterizer.
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- Jeff Butera created early prototypes of the bank layout.
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* * *
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[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
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[James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
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[VLSIDA]: https://vlsida.soe.ucsc.edu
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[VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
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[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
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[Github issues]: https://github.com/PrivateRAM/PrivateRAM/issues
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[Github pull request]: https://github.com/PrivateRAM/PrivateRAM/pulls
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[Github projects]: https://github.com/PrivateRAM/PrivateRAM/projects
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[email me]: mailto:mrg+openram@ucsc.edu
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[VLSIDA]: https://vlsida.soe.ucsc.edu
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[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/
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[Magic]: http://opencircuitdesign.com/magic/
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[Netgen]: http://opencircuitdesign.com/netgen/
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[Qflow]: http://opencircuitdesign.com/qflow/history.html
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[Ngspice]: http://ngspice.sourceforge.net/
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[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/
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[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
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[Ngspice]: http://ngspice.sourceforge.net/
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[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
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