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4,273 Commits 4 Branches 63 Tags 78 MiB
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4273 Commits

Author SHA1 Message Date
Hunter Nichols 5f954689a5 In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
Matt Guthaus 2ad38d1110 Merge branch 'dev' 2018-11-21 09:30:35 -08:00
Matt Guthaus e5dc4eddb7 Port coverage and badges to OpenRAM 2018-11-21 08:54:38 -08:00
Matt Guthaus 21fec02dc7 Remove job from coverage badge URL. 2018-11-21 06:38:39 -08:00
Matt Guthaus 3864e45aec Duh. Forgot coverage report. 2018-11-20 20:58:52 -08:00
Matt Guthaus c9f2b0e455 Revert source paths to build dir 2018-11-20 19:48:33 -08:00
Matt Guthaus e242d18dcb Specify period in artifact filename 2018-11-20 18:17:36 -08:00
Matt Guthaus 20a65fe7b2 Add source path with env variables 2018-11-20 17:47:18 -08:00
Matt Guthaus d34583093e Add coverage job to badges 2018-11-20 17:41:31 -08:00
Matt Guthaus 9a24ce8bc9 Add gitlab paths to combine different source locations 2018-11-20 17:39:37 -08:00
Matt Guthaus f1022d0cb0 Multiple stages to gitlab-ci. Combine coverage artifacts to generate html coverage. 2018-11-20 16:49:03 -08:00
Matt Guthaus 1659f66070 Add local badges 2018-11-20 16:02:11 -08:00
Matt Guthaus a4a97ceb27 Missing bracket 2018-11-20 15:52:46 -08:00
Matt Guthaus 0c045815d2 Add python badge 2018-11-20 15:51:17 -08:00
Matt Guthaus 05ee7745c6 Source tool setup before script 2018-11-20 15:42:46 -08:00
Matt Guthaus 043e468818 Forgot coverge run statement 2018-11-20 15:41:05 -08:00
Matt Guthaus 5eedce7dc3 Change pwd to backticks 2018-11-20 15:39:53 -08:00
Matt Guthaus 770e824c49 Add entire wqscript to yml file 2018-11-20 15:37:09 -08:00
Matt Guthaus 8fde15a7e3 Add coverage artifact 2018-11-20 15:25:00 -08:00
Matt Guthaus 0bb612d9e4 Remove tabs in yml file 2018-11-20 15:20:55 -08:00
Matt Guthaus b5d9a0e5ee Do only coverage with scn4m_subm 2018-11-20 15:19:36 -08:00
Matt Guthaus d6bcba4326 Add first attempt at code coverage. 2018-11-20 15:12:14 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Jesse Cirimelli-Low 29f19ad70f replaced absolute links with relative links 2018-11-20 12:27:54 -08:00
Jesse Cirimelli-Low 9ef5190d2e removed webserver files 2018-11-20 11:53:27 -08:00
Jesse Cirimelli-Low 7d070c2652 Added links to logos 2018-11-20 11:51:38 -08:00
Hunter Nichols 67977bab3e Fixed port issue in bank. Changed golden data due to netlist change. 2018-11-20 11:39:14 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 2f29ad5510 Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. 2018-11-19 22:13:58 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Hunter Nichols e8f1c19af6 Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00