 mrg
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71d86f88b0
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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mrg
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f2313d0c73
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Use default names for replica_column too
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2020-09-10 12:04:46 -07:00 |
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mrg
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3c0707e5d1
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Consistents of bl x port then br x port
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2020-09-09 13:38:13 -07:00 |
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mrg
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3062aba214
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Fix update to exclude bits with RBLs
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2020-09-09 13:03:05 -07:00 |
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mrg
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12fd60e8c3
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Fix pbitcell array test
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2020-09-09 12:02:09 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
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 Hunter Nichols
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af22e438f1
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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mrg
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8e91ec1770
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Add check_pins function
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2020-09-08 13:31:50 -07:00 |
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mrg
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1269bf6e16
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Global bitcell working
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2020-09-04 13:06:58 -07:00 |
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Hunter Nichols
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8bcbf005bf
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Merge branch 'dev' into characterizer_bug_fixes
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2020-09-04 02:25:01 -07:00 |
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Hunter Nichols
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500327d59b
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Fixed import in simulation and fixed names in functional
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2020-09-04 02:24:18 -07:00 |
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mrg
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1534295326
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Ground dummy lines in replica bitcell array
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2020-09-03 14:04:20 -07:00 |
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mrg
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f6f6242d68
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Ground dummy lines in replica bitcell array
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2020-09-03 10:45:28 -07:00 |
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Hunter Nichols
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d027632bdc
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Moved majority of code duplicated between delay and functional to simulation
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2020-09-02 14:22:18 -07:00 |
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mrg
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4ec47d8ee1
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Refactor global and local to be a bitcell_base_array
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2020-09-01 11:59:01 -07:00 |
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mrg
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c1c631abe1
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Global bitcell array passes LVS/DRC
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2020-09-01 10:57:49 -07:00 |
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mrg
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7bdce3ca9a
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Don't make dummy bitlines pins for simplicity
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2020-09-01 09:55:23 -07:00 |
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Hunter Nichols
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13b1d4613c
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Moved spice naming checking code from design to the spice base module
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2020-08-31 14:36:13 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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c1c1535210
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Merge branch 'wlbuffer' into dev
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2020-08-27 15:44:29 -07:00 |
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Hunter Nichols
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42f2ff679e
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Removed dead code from delay and base module related to characterization
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2020-08-27 15:40:41 -07:00 |
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mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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mrg
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da827d923f
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Merge branch 'wlbuffer' into dev
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2020-08-26 10:00:34 -07:00 |
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mrg
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c321d85595
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Fix syntax error for dual port
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2020-08-26 09:54:41 -07:00 |
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mrg
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e92337ddaf
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Separate get_ and get_all for bitlines and wordlines
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2020-08-25 17:08:48 -07:00 |
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mrg
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652f160aca
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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mrg
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bdb18b4cab
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Fix disconnected replica pins
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2020-08-25 14:51:49 -07:00 |
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mrg
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bd8bf9afd8
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Remove RBL label at top level of SRAM
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2020-08-25 14:42:21 -07:00 |
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mrg
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856cce1e62
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Add -json for detailed LVS output
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2020-08-25 13:58:28 -07:00 |
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mrg
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28bd93bf51
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Still working on array refactor
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2020-08-25 11:50:44 -07:00 |
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mrg
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8dee5520e0
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Standardize array names independent of bitcell
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2020-08-21 13:44:35 -07:00 |
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mrg
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b762580ee2
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Skip global test for now
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2020-08-19 11:36:21 -07:00 |
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mrg
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593a98e29a
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Update local bitcell array for dual port
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2020-08-19 11:35:55 -07:00 |
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mrg
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e215c0e016
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Drafting global bitcell array
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2020-08-18 16:30:55 -07:00 |
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mrg
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5776788574
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Order of wordlines and bitlines in bank
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2020-08-18 16:30:38 -07:00 |
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mrg
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224e359208
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Fix pin order for replica array
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2020-08-18 15:59:05 -07:00 |
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mrg
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f58fc6579f
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Rename local/global tests
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2020-08-18 15:58:44 -07:00 |
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mrg
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e3e4bac922
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Fix replica bitcell array for right only RBL
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2020-08-18 15:47:52 -07:00 |
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mrg
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59d65c46c3
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Fix bug in not adding RBLs in local bitcell array
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2020-08-18 15:11:10 -07:00 |
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mrg
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2643a96f97
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Order inputs wordline, bitline, supply
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2020-08-18 14:29:36 -07:00 |
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mrg
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b288bba43e
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Add global bitcell array test
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2020-08-18 14:29:23 -07:00 |
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mrg
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f98fbb175b
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Merge branch 'wlbuffer' into dev
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2020-08-18 10:06:52 -07:00 |
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mrg
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e37a9234cc
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Update replica column call to new refactor
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2020-08-18 09:14:50 -07:00 |
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mrg
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17504a7da3
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-18 09:01:41 -07:00 |
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mrg
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bc974ff78e
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Update replica column unit tests for new refactor
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2020-08-18 08:56:24 -07:00 |
|
 jcirimel
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9cecf367ee
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Merge branch 'dev' into pex
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2020-08-17 17:49:41 -07:00 |
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jcirimel
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714b57d48e
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Merge branch 'dev' into pex
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2020-08-17 17:48:21 -07:00 |
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mrg
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99e252d6d4
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Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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mrg
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b1e55f9072
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Add local bitcell array
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2020-08-17 15:14:42 -07:00 |
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mrg
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3a692e2846
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Comment updates
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2020-08-17 14:35:39 -07:00 |
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