|
base
|
Merge branch 'dev' into characterizer_bug_fixes
|
2020-09-04 02:25:01 -07:00 |
|
bitcells
|
update to new metal stack names
|
2020-07-31 05:27:19 -07:00 |
|
drc
|
PEP8 cleanup
|
2020-04-15 11:24:28 -07:00 |
|
example_configs
|
Fix 1w/1r example
|
2020-07-23 14:17:13 -07:00 |
|
modules
|
Merge branch 'dev' into characterizer_bug_fixes
|
2020-09-04 02:25:01 -07:00 |
|
tests
|
Fixed local bitcell array for single and dual port
|
2020-08-27 14:03:05 -07:00 |
|
verify
|
Merge branch 'wlbuffer' into dev
|
2020-08-25 15:50:08 -07:00 |
|
debug.py
|
DRC/LVS and errors fixes.
|
2020-06-30 07:16:05 -07:00 |
|
globals.py
|
OpenRAM 1.1.6
|
2020-07-13 16:26:25 -07:00 |
|
openram.py
|
Add words_per_row and others in config file.
|
2020-07-13 12:37:56 -07:00 |
|
options.py
|
Add words_per_row and others in config file.
|
2020-07-13 12:37:56 -07:00 |
|
sram_factory.py
|
Auto-generate port dependent cell names.
|
2020-06-05 15:09:22 -07:00 |
|
view_profile.py
|
Remove some flake8 errors/warnings.
|
2019-10-02 23:26:02 +00:00 |