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4909 Commits

Author SHA1 Message Date
SWalker 8ac30f4ef5 proper gds for nand 2023-10-31 23:24:21 -07:00
SWalker 416140d04a nand dup pin 2023-10-31 23:24:21 -07:00
SWalker 8c56478df3 more nand tweaks 2023-10-31 23:24:21 -07:00
SWalker 13459cb6dd boundary box tweaks on dec nand 2023-10-31 23:24:21 -07:00
SWalker 88782b0a58 rotated nand2_dec 2023-10-31 23:24:21 -07:00
SWalker 4bb586c949 decoder nand custom cell 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Sage Walker 0040efb86f workaround for magic drc in gf180 2023-10-31 23:24:21 -07:00
Sage Walker b0a0226e87 rom array compatability changes 2023-10-31 23:24:21 -07:00
Sage Walker 1255a81487 ROM binary file support 2023-10-31 23:24:21 -07:00
Sage Walker c09a981734 make pdk uses conda for gf180 with configure options for local pdk sources 2023-10-31 23:24:21 -07:00
Hadir Khan 698020301c updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
Hadir Khan 7ce11eba52 added pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
hadirkhan10 b9fd172e44 corrected the pin mapping 2023-10-31 23:24:21 -07:00
hadirkhan10 de7a248ff0 added the cell property definitions 2023-10-31 23:24:21 -07:00
Hadir Khan 81b62ab13b added gf180mcu as the test tech target 2023-10-31 23:24:21 -07:00
Hadir Khan 8a5b0b4898 updated the open_pdks commit and added the gf180 pdk build target 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a904874978 passing gf180 parameterized gate tests 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low d18a4f8c7c additional tech commits 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a18d62c430 rename gf180 to gf180mcu 2023-10-31 23:24:21 -07:00
mrg 06058e1b87 Initial files for gf180 2023-10-31 23:24:21 -07:00
vlsida-bot decfd7ff4f Bump version: 1.2.40 -> 1.2.41 2023-11-01 02:31:22 +00:00
Jesse Cirimelli-Low 788d7e5474 fix VPB/VNB pins not being found 2023-10-31 18:07:35 -07:00
Mik Igor aa2cf88870
Fix tabs/spaces in globals.py 
Some tabs/extra spaces were inserted accidentally by GitHub text editor in the tech_name param validation, so has to remove them.
 2023-10-27 01:35:04 +02:00
Mik Igor 173e47ae45
Validate tech_name in config file iterating over technology dir 
We're now validating the tech_name param specified by the user in the config file listing all the subfolders present in the technology folder. If the technology specified is not present as folder, we will emit an error and quit.
 2023-10-27 01:29:27 +02:00
Mik Igor 5811c5ce99
FIX: scn3me_subm typo 
Fixed incorrect tech_name "scn3m_subm" (correct is "scn3me_subm", note the 3mE).
 2023-10-27 00:49:31 +02:00
Mik Igor 189824429c
Add freepdk45 to debug error in tech_name validation 
Ooops, I forgot to add the freepdk45 mention in the debug.log string
 2023-10-27 00:45:32 +02:00
Mik Igor 123e43e942
Add freepdk45 to tech_name validation in compiler/globals.py 
Forgot to add the freepdk45 tech_name in validation
 2023-10-27 00:40:55 +02:00
Mik Igor ce2b11ebd9
Validate tech_name param in compiler/globals.py 
We need to pre-validate the tech_name param in the config file or python will comply with a non-very-descriptive message that can confuse the user about where's the problem.
 2023-10-26 23:53:03 +02:00
vlsida-bot 3113798b13 Bump version: 1.2.39 -> 1.2.40 2023-10-06 02:12:26 +00:00
Eren Dogan fe379297be Add timestamps to the log file 2023-10-05 14:55:05 -07:00
vlsida-bot 6a6ac026db Bump version: 1.2.38 -> 1.2.39 2023-09-28 19:50:40 +00:00
Sam Crow a5412902c6 all control logic tests pass now 2023-09-27 16:38:57 -07:00
vlsida-bot 1b13d4369e Bump version: 1.2.37 -> 1.2.38 2023-09-27 23:25:24 +00:00
Sam Crow bf49ea744e force multi-delay chain pinouts to be user configurable 2023-09-27 13:15:45 -07:00
vlsida-bot c47ec37473 Bump version: 1.2.36 -> 1.2.37 2023-09-26 20:04:03 +00:00
Sam Crow 0a3889a2a6 Revert "use new magic version with drc catchup fix" 
This reverts commit ad2468cc26.
 2023-09-26 11:37:34 -07:00
Sam Crow 5b282df667 Revert "add drc style drc(full) to run_drc.sh on Tim Edwards recommondation" 
This reverts commit c4a14b9354.
 2023-09-26 11:37:04 -07:00
Sam Crow c4a14b9354 add drc style drc(full) to run_drc.sh on Tim Edwards recommondation 2023-09-25 14:14:27 -07:00
Sam Crow ad2468cc26 use new magic version with drc catchup fix 2023-09-25 14:08:38 -07:00
vlsida-bot 2e55385cd6 Bump version: 1.2.35 -> 1.2.36 2023-09-20 23:25:59 +00:00
Eren Dogan 3b6cc2f3a8 Hardcode tool versions in install_conda.sh 2023-09-20 14:58:58 -07:00
vlsida-bot 1a8c27c549 Bump version: 1.2.34 -> 1.2.35 2023-09-09 22:09:16 +00:00
Eren Dogan b3e1a163d0 Fix derouting wires in the gridless router 2023-09-09 13:32:16 -07:00
vlsida-bot 9c66473cc9 Bump version: 1.2.33 -> 1.2.34 2023-09-07 06:07:59 +00:00
Eren Dogan 995cc4f60f Fix typo 2023-09-06 21:38:19 -07:00
Eren Dogan 099869d4c9 Fix typos 2023-09-03 18:35:07 -07:00
Eren Dogan 3f2d61a0fa Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108) 2023-09-03 18:21:31 -07:00
vlsida-bot 1a25fcf9a5 Bump version: 1.2.32 -> 1.2.33 2023-09-02 18:43:35 +00:00
Eren Dogan abb12bd785 Increase non-preferred direction cost in router 2023-09-02 08:00:58 -07:00