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OpenRAM
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3545 Commits

Author SHA1 Message Date
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 2f29ad5510 Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. 2018-11-19 22:13:58 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Hunter Nichols e8f1c19af6 Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 82a5fbd4d4 Set theme jekyll-theme-dinky 2018-11-16 08:56:44 -08:00
Matt Guthaus a1526c0394 Set theme jekyll-theme-midnight 2018-11-16 08:54:45 -08:00
Matt Guthaus 935cc5109b Set theme jekyll-theme-hacker 2018-11-16 08:37:54 -08:00
Matt Guthaus ee9aad1b21 Errors in contributors. 2018-11-16 08:26:09 -08:00
Matt Guthaus 26814f92ef Clarify basic setup instructions. 2018-11-16 08:25:04 -08:00
Matt Guthaus 63038480fc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-16 08:23:54 -08:00
Matt Guthaus ff67e772fa Fix extra escape in README 2018-11-15 17:28:06 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 43472dfa46 Modify sense amp to cross coupled inverter 2018-11-15 16:55:18 -08:00
Matt Guthaus 65d341619c Fix typos in README 2018-11-15 15:48:15 -08:00
Matt Guthaus efb0cf25bf Update link to commits for each branch 2018-11-15 15:35:00 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Matt Guthaus 347a68074c Merge remote-tracking branch 'origin/dev' into multiport_layout 2018-11-15 15:25:34 -08:00
Matt Guthaus e0c679054d Add new README.md with badges. 2018-11-15 15:15:37 -08:00
Matt Guthaus c3670fc91d Add new README.md with badges. 2018-11-15 15:09:38 -08:00
Matt Guthaus 5cd89fd7da Add image and further README details 2018-11-15 14:54:56 -08:00
Matt Guthaus 61eb281038 More README.md updates 2018-11-15 14:38:28 -08:00
Matt Guthaus 7b53dffbc6 Plural error 2018-11-15 14:29:32 -08:00
Matt Guthaus 43a7c2e334 Add more information to README.md file 2018-11-15 14:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Matt Guthaus f87c72fe77 Merge branch 'dev' into multiport_layout 2018-11-15 12:59:15 -08:00
Matt Guthaus a74baccef2 Convert link to relative commits 2018-11-15 12:49:10 -08:00
Matt Guthaus 89e5ce8a95 Convert link to relative commits 2018-11-15 12:47:47 -08:00
Matt Guthaus d3803d8c81 Convert link to relative commits 2018-11-15 12:46:19 -08:00
Matt Guthaus 7819844269 Remove broken artifact link 2018-11-15 12:42:13 -08:00
Matt Guthaus cccd815817 Add read-only guest token for pipeline badge access 2018-11-15 12:14:35 -08:00