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OpenRAM
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1251 Commits

Author SHA1 Message Date
Matt Guthaus 61eb281038 More README.md updates 2018-11-15 14:38:28 -08:00
Matt Guthaus 7b53dffbc6 Plural error 2018-11-15 14:29:32 -08:00
Matt Guthaus 43a7c2e334 Add more information to README.md file 2018-11-15 14:26:59 -08:00
Matt Guthaus a74baccef2 Convert link to relative commits 2018-11-15 12:49:10 -08:00
Matt Guthaus 89e5ce8a95 Convert link to relative commits 2018-11-15 12:47:47 -08:00
Matt Guthaus d3803d8c81 Convert link to relative commits 2018-11-15 12:46:19 -08:00
Matt Guthaus 7819844269 Remove broken artifact link 2018-11-15 12:42:13 -08:00
Matt Guthaus cccd815817 Add read-only guest token for pipeline badge access 2018-11-15 12:14:35 -08:00
Matt Guthaus 487e61457b Some small updates to README.md 2018-11-15 11:33:15 -08:00
Matt Guthaus 890d93d776 Update image paths. Add download badge. 2018-11-15 11:20:40 -08:00
Matt Guthaus f3a1acb617 Rename badge file 2018-11-15 11:08:36 -08:00
Matt Guthaus 6e40e2b9c7 Add initial README.md features with badges and links. 2018-11-15 11:07:04 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Matt Guthaus 01ceedb348 Only check number of ports when doing layout. 2018-11-13 16:42:25 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Matt Guthaus aa779a7f82 Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
Matt Guthaus 732f35a362 Change channel router to route from bottom up to simplify code. 2018-11-11 12:25:53 -08:00
Matt Guthaus 791d74f63a Fix wrong exception handling that depended on order. Replaced with if/else instead. 2018-11-11 12:02:42 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Matt Guthaus 65b6bfd5e7 Change os to shutils 2018-11-10 10:06:33 -08:00
Matt Guthaus 3b6b93e2ca Save gds file in testutils when fail to figure out randomness in regression CI 2018-11-10 10:05:27 -08:00
Matt Guthaus de61630962 Expand blocked pins to neighbor grid cells. 2018-11-09 14:25:10 -08:00
Matt Guthaus 11873c03cd Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-09 11:12:46 -08:00
Matt Guthaus 83aadc47c9 Remove layer 230 labels from library cells 2018-11-09 11:12:31 -08:00
Matt Guthaus c5b408ae2d Add router output message 2018-11-09 11:10:40 -08:00
Matt Guthaus 05c25eb506 Remove layer 230 labels from library cells 2018-11-09 11:08:20 -08:00
Matt Guthaus 9fe64b486c Remove layer 230 labels from library cells 2018-11-09 11:02:19 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus cc619084c7 Clean up psingle_bank_test 2018-11-09 09:34:34 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Matt Guthaus 6aff552c0a Merge branch 'multiport_layout' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-09 08:53:27 -08:00
Matt Guthaus 8f3fa0e2f6 Fix blocked pin debug output. 2018-11-09 08:52:05 -08:00
Matt Guthaus 9c8d5395ff Update leakage data for scn4m 2018-11-08 18:16:01 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5d684b02e0 Leakage changed in ngspice test. 2018-11-08 18:00:09 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Matt Guthaus d03c9d5294 Fix write bl name list in replica bitline 2018-11-08 17:02:20 -08:00
Matt Guthaus fd5cd675ac Horizontal increments top down. 2018-11-08 17:01:57 -08:00
Matt Guthaus 18fbf30b46 Convert col decoder select routing to channel route. 2018-11-08 16:53:58 -08:00
Matt Guthaus e28978180f Vertical channel routes go from left right. Horizontal go bottom up. 2018-11-08 16:49:02 -08:00
Matt Guthaus ef2ed9a92c Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
Matt Guthaus 5d733154e9 Refactor bank to allow easier multiport. 2018-11-08 15:18:51 -08:00
Michael Timothy Grimes 455ef7ef99 Merge branch 'multiport' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-08 12:33:03 -08:00