jcirimel
5d5ed552e3
Merge branch 'dev' into discrete_models
2020-06-06 01:48:06 -07:00
mrg
0837432d45
Wordline route layers and (optional) via.
2020-06-05 16:47:22 -07:00
jcirimel
9857a3f7e7
Merge branch 'dev' into discrete_models
2020-06-05 16:47:01 -07:00
mrg
5514996708
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
mrg
00b51f5464
PEP8 format replica_bitcell_array
2020-06-05 13:49:32 -07:00
mrg
4fef632dce
Fix syntax error
2020-06-05 12:13:41 -07:00
mrg
a62b85a6b1
Update mirroring in port_data for bitcell mirrored arrays
2020-06-05 11:29:31 -07:00
mrg
2e7f9395f2
Rename 05 test to 14
2020-06-05 09:57:16 -07:00
mrg
68ffb94d2e
Rename 05 test to 14
2020-06-05 09:55:57 -07:00
mrg
fb3acae908
PEP8 format testutils.
2020-06-05 09:44:30 -07:00
jcirimel
08f6bd8d24
optimize tx binning for area
2020-06-05 02:53:03 -07:00
mrg
e14deff3d1
Fixed offset in port_data
2020-06-04 16:03:39 -07:00
mrg
2fcecb7227
Variable zjog. 512 port address test. s8 port address working.
2020-06-04 16:01:32 -07:00
mrg
e06dc3810a
Move precharge pin to bottom
2020-06-04 12:12:19 -07:00
mrg
717188f85c
Change L shape of rbl route
2020-06-04 11:03:39 -07:00
mrg
7aafa43897
Connect RBL to bottom of precharge cell
2020-06-04 10:22:52 -07:00
mrg
249b5355ba
Adjust rbl route
2020-06-03 17:08:04 -07:00
mrg
77c95b28da
Rename precharge test
2020-06-03 16:39:46 -07:00
mrg
3927c62e32
Undo extra space due to nwell spacing
2020-06-03 16:39:33 -07:00
mrg
b2b7e7800b
Undo same bitline pitch
2020-06-03 16:39:05 -07:00
mrg
4183638f03
Align precharge bitlines with col mux
2020-06-03 16:05:57 -07:00
mrg
4bc1e9a026
Fix the bitline spacing in the column mux to a constant.
2020-06-03 15:47:03 -07:00
mrg
3b1fe26d25
Spacing between decoder and driver for s8
2020-06-03 14:33:30 -07:00
mrg
e93f3f1d2e
Add 1rw_1r tests
2020-06-03 14:30:15 -07:00
mrg
b78166c044
Merge branch 'dev' into tech_migration
2020-06-03 14:08:22 -07:00
Joey Kunzler
7a602b75a4
keep dev routing changes to hierarchy_layout
2020-06-03 12:54:15 -07:00
Joey Kunzler
6430aad857
Merge branch 'dev' into s8_update
2020-06-03 11:53:33 -07:00
mrg
38f5e8b865
Add col mux tests for multiport
2020-06-03 10:01:02 -07:00
mrg
34209dac3d
A port option for correct mirroring in port_data.
2020-06-02 16:50:07 -07:00
Joey Kunzler
84021c9ccb
merge conflict 2 - port data
2020-06-02 16:32:08 -07:00
Joey Kunzler
001bf1b827
merge conflict - port data
2020-06-02 14:15:39 -07:00
mrg
fce8e878b9
Add port to col mux and simplify route with computation to fix mirror bug.
2020-06-02 13:57:41 -07:00
mrg
fdf51c5a00
Add port option to precharge array
2020-06-02 11:44:22 -07:00
mrg
f1b7b91b1a
Use non-channel route for s8 port_data
2020-06-02 11:43:57 -07:00
mrg
45b0601e4b
Fix via directions in s8 col mux
2020-06-02 11:43:31 -07:00
mrg
a1c7474f80
Revert to channel route of bitlines
2020-06-02 10:08:53 -07:00
mrg
620604603c
Fixed offset jogs
2020-06-02 10:08:37 -07:00
mrg
e69b665689
Flatten pbitcell_1 too
2020-06-02 09:31:43 -07:00
mrg
b0aa70ffda
Fix precharge vdd route layer
2020-06-02 09:23:27 -07:00
Joey Kunzler
b39579c109
temp drc fix for regression tests
2020-06-01 20:55:15 -07:00
mrg
9ecf98a4c3
SRAM factory uses default name for first instance even if it has arguments.
2020-06-01 16:46:22 -07:00
mrg
b3b03d4d39
Hard cells can accept height parameter too.
2020-06-01 16:46:00 -07:00
mrg
496a24389c
Remove prints
2020-05-29 16:57:47 -07:00
mrg
82dc937768
Add missing vias by using via stack function
2020-05-29 16:53:47 -07:00
Joey Kunzler
b00163e4e1
lvs fix for regression tests
2020-05-29 13:50:34 -07:00
mrg
4a67f7dc71
Thin-cell decoder changes.
...
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
2020-05-29 10:36:07 -07:00
Joey Kunzler
218a553ac5
fix for replica column mirroring over y
2020-05-28 20:31:21 -07:00
Joey Kunzler
7505fa5aef
update for end caps
2020-05-27 20:03:11 -07:00
Joey Kunzler
9a6b38b67e
merge conflict
2020-05-26 16:03:36 -07:00
mrg
a305d788d7
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
jcirimel
mrg
Joey Kunzler