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OpenRAM
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1796 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 5778901cfe pull bitline labels to top level spice 2020-01-20 12:16:30 +00:00
jcirimel 364842569a fix s_en in stim 2020-01-16 12:16:49 -08:00
jcirimel 075bf0d841 label bitcell in stim, add s_en top level to stim 2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low 2733c3bf3f fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
Jesse Cirimelli-Low 05ab018ffc strip padding character from gds reading 2020-01-07 00:01:32 +00:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Jesse Cirimelli-Low 88d3da0b4a fix control logic pex labels with multiport 2019-12-18 12:45:12 +00:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
vagrant 67c768d22c Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
Hunter Nichols d722311822 Merge branch 'dev' into update_scmos_models 2019-10-03 13:16:32 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus cbbcb97a10 Merge branch 'dev' into feedthru 2019-09-27 09:42:51 -07:00
Matt Guthaus 99507ba5c5 Remove rbl_bl_delay_bar from w_en logic inputs. 2019-09-07 23:22:01 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus 322af0ec09 Remove sense enable during writes 2019-09-07 20:04:48 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus 93c89895c9 Remove unused test structures 2019-09-06 14:58:47 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 6bee66f9dc Forgot to add cs_bar to rw port rails. 2019-09-06 09:29:23 -07:00
Matt Guthaus 969cca28e4 Enable sensing during writes. Need to add dedicated test. 2019-09-06 07:16:50 -07:00
jsowash 1c65b90c70 Merge branch 'dev' into add_wmask 2019-09-05 09:15:05 -07:00
Matt Guthaus 678b2cc3fa Fix functional test clk name 2019-09-04 18:59:08 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
jsowash 8c33749223 Uncommented offset_all_coordinates. 2019-09-04 16:41:27 -07:00
jsowash febc053587 Moved SRAM macro in LEF file to origin and removed poly. 2019-09-04 16:11:12 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 8c601ce939 Model tests don't need layout 2019-09-04 16:06:12 -07:00
Matt Guthaus c5568e86fe Enable spice and don't purge option to test 30 2019-09-04 14:33:25 -07:00
jsowash fbecb9bc02 Added poly to LEF files. 2019-09-04 14:06:17 -07:00
jsowash d6e7047e2f Added metal4 to lef files since it's now used with a wmask. 2019-09-04 13:04:51 -07:00
Matt Guthaus eadb5d5e48 Allow gds file for front end with new options 2019-09-04 10:26:54 -07:00
jsowash 496a9919b8 Added wmask as a type group to .lib. 2019-09-04 09:45:11 -07:00
jsowash 452cc5e443 Added wmask to lib.py. 2019-09-04 09:29:45 -07:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash abb86c338b Added port specification. 2019-09-03 14:52:43 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
jsowash 01bdea23ae Merge branch 'add_wmask' of https://github.com/VLSIDA/PrivateRAM into add_wmask 2019-09-03 11:50:57 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
jsowash 4a8ec7a687 Added 2 port test for wmask. 2019-09-03 11:49:37 -07:00