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OpenRAM
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2,262 Commits 4 Branches 63 Tags 78 MiB
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40 Commits

Author SHA1 Message Date
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
Matt Guthaus 53d0544291 Minor cleanup and additional assertion checking. 2019-08-21 08:50:12 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash a28c9fed8b Fixed bug for more than 2 wmasks and changed test to test 4 wmasks. 2019-08-16 14:27:44 -07:00
jsowash d02ea06ff2 Added method to route between the output of wmask AND array and en of write driver. 2019-08-16 14:12:41 -07:00
jsowash aaa1e3a614 Added change to route wmask en between driver and AND gates. Need to apply it to all cases. 2019-08-16 10:23:51 -07:00
jsowash 92e0671e15 Removed DRC error with AND array in freepdk45 and moved pin on en_{} pin in port data. 2019-08-15 12:36:17 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash 2573b5f48b Fixed merge conflict. 2019-08-11 14:39:36 -07:00
jsowash d259efbcda Connected wdriver_sel between write_mask_and_array and write_driver_array. 2019-08-11 14:33:08 -07:00
Matt Guthaus e5618b88af Don't add sense amp to write only port. Fix write_and None define. 2019-08-11 08:46:36 -07:00
jsowash 59e5441aef Added write mask to write driver array 2019-08-08 08:46:58 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
jsowash abb9af0ea8 Added layout pins for wmask_and_array 2019-08-07 09:33:19 -07:00
jsowash a6bb410560 Begin implementing a write mask layout as the port data level. 2019-08-07 09:12:21 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus 52029d8e48 Fix incorrect port_data BL pin name. 2019-07-27 06:11:45 -07:00
Matt Guthaus 179efe4d04 Fix bitline names in merge error 2019-07-26 22:03:50 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 5452ed69e7 Always have a precharge. 2019-07-25 10:31:39 -07:00
jsowash 2b29e505e0 Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks. 2019-07-22 12:44:35 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
jsowash 082decba18 Temporarily made the functional tests write/read only all 0's or 1's 2019-07-18 15:26:38 -07:00
jsowash 720739a192 Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask 2019-07-17 11:04:17 -07:00
jsowash ea2f786dcf Redefined write_size inrecompute_sizes() to take the new word_size() 2019-07-15 14:41:26 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
jsowash dfa2b29b8f Begin adding wmask netlist and spice tests. 2019-07-12 10:34:29 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
mrg dd62269e0b Some cleanup 2019-07-05 08:18:58 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00