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Added write mask to write driver array

This commit is contained in:
jsowash 2019-08-08 08:46:58 -07:00
parent 9409f60237
commit 59e5441aef
3 changed files with 33 additions and 32 deletions
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32
compiler/modules/port_data.py
View File

@ -110,7 +110,7 @@ class port_data(design.design):
def route_layout(self):
""" Create routing amoung the modules """
""" Create routing among the modules """
self.route_data_lines()
self.route_layout_pins()
self.route_supplies()
@ -124,7 +124,8 @@ class port_data(design.design):
""" Route the bitlines depending on the port type rw, w, or r. """
if self.port in self.readwrite_ports:
# write_driver -> sense_amp -> (column_mux) -> precharge -> bitcell_array
# (write_mask_and ->) write_driver -> sense_amp -> (column_mux ->) precharge -> bitcell_array
self.route_write_mask_and(self.port)
self.route_write_driver_in(self.port)
self.route_sense_amp_out(self.port)
self.route_write_driver_to_sense_amp(self.port)
@ -136,7 +137,8 @@ class port_data(design.design):
self.route_sense_amp_to_column_mux_or_precharge_array(self.port)
self.route_column_mux_to_precharge_array(self.port)
else:
# write_driver -> (column_mux ->) precharge -> bitcell_array
# (write_mask_and ->) write_driver -> (column_mux ->) precharge -> bitcell_array
self.route_write_mask_and(self.port)
self.route_write_driver_in(self.port)
self.route_write_driver_to_column_mux_or_precharge_array(self.port)
self.route_column_mux_to_precharge_array(self.port)
@ -437,26 +439,26 @@ class port_data(design.design):
self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
def route_write_mask_and_in(self, port):
def route_write_mask_and(self, port):
""" Add pins for the write mask and array output """
for bit in range(self.num_wmasks):
wmask_out_name = "wmask_out_{}".format(bit)
wdriver_sel_name = "wdriver_sel_{}".format(bit)
self.copy_layout_pin(self.write_mask_and_array_inst, wmask_out_name, wdriver_sel_name)
# for bit in range(self.num_wmasks):
# wmask_out_name = "wmask_out_{}".format(bit)
# wdriver_sel_name = "wdriver_sel_{}".format(bit)
# self.copy_layout_pin(self.write_mask_and_array_inst, wmask_out_name, wdriver_sel_name)
for bit in range(self.num_wmasks):
wmask_in_name = "wmask_in_{}".format(bit)
bank_wmask_name = "bank_wmask_{}".format(bit)
self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name)
# for bit in range(self.num_wmasks):
# wdriver_sel_pin = self.write_mask_and_array_inst.get_pin("wdriver_sel_{}".format(bit))
# self.add_layout_pin_rect_center(text="wdriver_sel_{0}".format(bit),
# layer=wdriver_sel_pin.layer,
# offset=wdriver_sel_pin.center(),
# height=wdriver_sel_pin.height(),
# width=wdriver_sel_pin.width())
for bit in range(self.num_wmasks):
wdriver_sel_pin = self.write_mask_and_array_inst.get_pin("wmask_out_{}".format(bit))
self.add_layout_pin_rect_center(text="wdriver_sel_{0}".format(bit),
layer=wdriver_sel_pin.layer,
offset=wdriver_sel_pin.center(),
height=wdriver_sel_pin.height(),
width=wdriver_sel_pin.width())
def route_column_mux_to_precharge_array(self, port):

25
compiler/modules/write_driver_array.py
View File

@ -49,7 +49,6 @@ class write_driver_array(design.design):
self.width = self.columns * self.bitcell.width
else:
self.width = self.columns * self.driver.width
self.height = self.driver.height
self.place_write_array()
@ -63,9 +62,9 @@ class write_driver_array(design.design):
for i in range(self.word_size):
self.add_pin("bl_{0}".format(i), "OUTPUT")
self.add_pin("br_{0}".format(i), "OUTPUT")
if self.write_size != None:
if self.write_size is not None:
for i in range(self.num_wmasks):
self.add_pin("en_{}".format(i), "INPUT")
self.add_pin("en_{0}".format(i), "INPUT")
else:
self.add_pin("en", "INPUT")
self.add_pin("vdd", "POWER")
@ -111,10 +110,10 @@ class write_driver_array(design.design):
driver_spacing = self.bitcell.width
else:
driver_spacing = self.driver.width
for i in range(0,self.columns,self.words_per_row):
index = int(i/self.words_per_row)
base = vector(i * driver_spacing,0)
index = int(i/self.words_per_row)
base = vector(i * driver_spacing, 0)
self.driver_insts[index].place(base)
@ -152,18 +151,18 @@ class write_driver_array(design.design):
offset=pin_pos)
if self.write_size is not None:
for bit in range(self.num_wmasks):
self.add_layout_pin(text="en_{}".format(bit),
layer="metal1",
offset=self.driver_insts[bit*(self.write_size-1)].get_pin("en").ll().scale(0,1),
width=self.width,
height=drc('minwidth_metal1'))
else:
en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
self.add_layout_pin(text="en_{0}".format(bit),
layer=en_pin.layer,
offset=en_pin.ll(),
width=1.75*self.write_size*en_pin.width(),
height=en_pin.height())
self.add_layout_pin(text="en",
layer="metal1",
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
width=self.width,
height=drc('minwidth_metal1'))
def get_w_en_cin(self):

8
compiler/modules/write_mask_and_array.py
View File

@ -123,9 +123,9 @@ class write_mask_and_array(design.design):
offset=pin_pos)
# def get_w_en_cin(self):
# """Get the relative capacitance of all the enable connections in the bank"""
# # The enable is connected to a nand2 for every row.
# return self.driver.get_w_en_cin() * len(self.driver_insts)
def get_cin(self):
"""Get the relative capacitance of all the input connections in the bank"""
# The enable is connected to an and2 for every row.
return self.and2.get_cin() * len(self.and2_insts)