 mrg
|
4a8e0cdabb
|
Add top-level pin functionality
|
2021-05-26 15:04:52 -07:00 |
|
|
mrg
|
9c01e22281
|
Prioritize Xyce.
|
2021-05-21 12:05:10 -07:00 |
|
|
mrg
|
f856a44376
|
Restrict to direct KLU solver
|
2021-05-21 12:04:26 -07:00 |
|
|
mrg
|
fc17a1ff45
|
Xyce can be capital or lower case
|
2021-05-21 12:04:26 -07:00 |
|
|
mrg
|
d51ec4fe45
|
Add Xyce tests
|
2021-05-21 12:04:26 -07:00 |
|
|
mrg
|
eadf7eedc5
|
Prioritize Xyce to last until bugs resolved.
|
2021-05-21 10:01:37 -07:00 |
|
|
mrg
|
7c001732b1
|
Add destination file as dot file
|
2021-05-18 14:54:13 -07:00 |
|
|
mrg
|
191b382171
|
Change magic to use OPENRAM_MAGICRC if defined.
|
2021-05-18 13:27:11 -07:00 |
|
|
mrg
|
3abebe4068
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
|
mrg
|
7534610cdd
|
Add MPI capability for Xyce threading.
|
2021-05-14 11:45:37 -07:00 |
|
|
mrg
|
507ad9f33d
|
Change sim threads to 3.
|
2021-05-14 11:45:10 -07:00 |
|
|
mrg
|
67a67111a6
|
Initial Xyce support.
|
2021-05-14 11:28:29 -07:00 |
|
|
mrg
|
3959cf73d1
|
Remove setup/hold measure and compute it directly.
|
2021-05-14 10:11:14 -07:00 |
|
|
mrg
|
9555b52aaa
|
Remove setup/hold measure and compute it directly.
|
2021-05-14 10:01:10 -07:00 |
|
|
mrg
|
d43edd95e4
|
Update golden tests for verilog
|
2021-05-06 19:56:22 -07:00 |
|
|
mrg
|
57c58ce4a5
|
Always route data dff on m3 stack.
|
2021-05-06 17:14:39 -07:00 |
|
|
mrg
|
453f260ca2
|
Add commented save npz file for intern
|
2021-05-06 17:14:27 -07:00 |
|
|
mrg
|
e995e61ea4
|
Fix Verilog module typo. Adjust RBL route.
|
2021-05-06 14:32:47 -07:00 |
|
|
mrg
|
c057490923
|
Delay chain should have same height cells as control logic to align supplies.
|
2021-05-05 15:45:28 -07:00 |
|
|
mrg
|
789a8a1cf0
|
Update golden verilog results
|
2021-05-05 15:37:27 -07:00 |
|
|
mrg
|
f677c8a88d
|
Fix predecoder offset after relocating bank offset
|
2021-05-05 14:44:05 -07:00 |
|
|
mrg
|
120c4de5ad
|
Fix placement of delay chain to align with control logic rows.
|
2021-05-05 14:21:53 -07:00 |
|
|
mrg
|
b3948121df
|
Default supply routing is tree.
|
2021-05-05 14:04:24 -07:00 |
|
|
mrg
|
f48b0b8f41
|
Add left stripe power routes to tree router as option.
|
2021-05-05 13:45:12 -07:00 |
|
|
mrg
|
d3f4810d1b
|
Add error with zero length labels on GDS write.
|
2021-05-05 13:44:31 -07:00 |
|
|
mrg
|
2243761500
|
Must transitively cut blockages until no more.
|
2021-05-05 13:44:06 -07:00 |
|
|
mrg
|
19ea33d43d
|
Move delay line module down.
|
2021-05-04 16:42:42 -07:00 |
|
|
mrg
|
a0e263b14a
|
Add vdd/gnd pins to the side.
|
2021-05-03 15:14:15 -07:00 |
|
|
mrg
|
98fb34c44c
|
Add conditional power pins to Verilog model.
|
2021-04-30 14:15:32 -07:00 |
|
|
mrg
|
fc6e6e1ec7
|
Add via when write driver supply is different layer
|
2021-04-28 15:16:26 -07:00 |
|
|
mrg
|
03e0c14ab2
|
Move write driver supply to m1 rather than pin layer
|
2021-04-28 10:13:33 -07:00 |
|
|
mrg
|
467aaa708d
|
Add noninverting logic function to custom decoder cells.
|
2021-04-22 16:13:54 -07:00 |
|
|
mrg
|
d018963866
|
Specify ImportError to see other errors
|
2021-04-22 16:13:32 -07:00 |
|
|
mrg
|
01f4ad7a11
|
Add sky130 config examples
|
2021-04-22 13:53:23 -07:00 |
|
|
mrg
|
a111ecb74c
|
Fix extra indent that made openlane fail.
|
2021-04-22 13:05:51 -07:00 |
|
|
mrg
|
261d31312a
|
Merge branch 'sky130_fixes' of github.com:VLSIDA/PrivateRAM into sky130_fixes
|
2021-04-22 09:45:03 -07:00 |
|
|
mrg
|
35fcb3f631
|
Abstracted LEF added. Params for array wordline layers.
|
2021-04-22 09:44:25 -07:00 |
|
|
mrg
|
15b0583ff2
|
Add custom parameter for wordline layer
|
2021-04-22 09:42:49 -07:00 |
|
 Hunter Nichols
|
b8c7fcf182
|
Removed measurement check which conflicts with multiport memories
|
2021-04-21 15:53:27 -07:00 |
|
|
mrg
|
1190eb76e8
|
Add over-ride languages
|
2021-04-21 14:15:24 -07:00 |
|
|
mrg
|
9f0ae7552c
|
Update download link to stable.zip link.
|
2021-04-21 13:00:49 -07:00 |
|
|
mrg
|
419836411c
|
Fix missing via for global wordlines.
|
2021-04-21 11:33:18 -07:00 |
|
|
mrg
|
f45efe3db6
|
Abstracted LEF added. Params for array wordline layers.
|
2021-04-21 11:04:01 -07:00 |
|
|
mrg
|
584349c911
|
Add custom parameter for wordline layer
|
2021-04-21 11:04:01 -07:00 |
|
|
mrg
|
3421055ec4
|
Update python requirements
|
2021-04-21 10:39:15 -07:00 |
|
|
mrg
|
f61904e864
|
Crop boundary of logo
|
2021-04-21 10:33:19 -07:00 |
|
|
mrg
|
4604a5034e
|
Abstracted LEF added. Params for array wordline layers.
|
2021-04-21 10:07:37 -07:00 |
|
|
mrg
|
17f87c50a7
|
Add custom parameter for wordline layer
|
2021-04-19 14:23:14 -07:00 |
|
|
mrg
|
0b7b87e0e6
|
Merge branch 'sky130_fixes' of github.com:VLSIDA/PrivateRAM into sky130_fixes
|
2021-04-19 13:24:39 -07:00 |
|
|
mrg
|
23aa69ec40
|
Add logo and remove master text from README.
|
2021-04-19 13:24:18 -07:00 |
|