Add custom parameter for wordline layer

compiler/base/custom_layer_properties.py

@@ -123,6 +123,12 @@ class _wordline_driver:
         self.vertical_supply = vertical_supply
 
 
+class _bitcell_array:
+    def __init__(self,
+                 wordline_layer):
+        self.wordline_layer = wordline_layer
+
+
 class layer_properties():
     """
     This contains meta information about the module routing layers. These
@@ -159,6 +165,10 @@ class layer_properties():
 
         self._wordline_driver = _wordline_driver(vertical_supply=False)
 
+        self._local_bitcell_array = _bitcell_array(wordline_layer="m3")
+
+        self._global_bitcell_array = _bitcell_array(wordline_layer="m3")
+
     @property
     def bank(self):
         return self._bank
@@ -191,3 +201,11 @@ class layer_properties():
     def wordline_driver(self):
         return self._wordline_driver
 
+    @property
+    def global_bitcell_array(self):
+        return self._global_bitcell_array
+
+    @property
+    def local_bitcell_array(self):
+        return self._local_bitcell_array
+

compiler/modules/global_bitcell_array.py

@@ -11,6 +11,7 @@ from sram_factory import factory
 from vector import vector
 import debug
 from numpy import cumsum
+from tech import layer_properties as layer_props
 
 
 class global_bitcell_array(bitcell_base_array.bitcell_base_array):
@@ -223,11 +224,20 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
                     new_name = "{0}_{1}".format(base_name, col + col_value)
                     self.copy_layout_pin(inst, pin_name, new_name)
 
+        # Add the global word lines
+        wl_layer = layer_props.global_bitcell_array.wordline_layer
+
         for wl_name in self.local_mods[0].get_inputs():
+            for local_inst in self.local_insts:
+                wl_pin = local_inst.get_pin(wl_name)
+                self.add_via_stack_center(from_layer=wl_pin.layer,
+                                          to_layer=wl_layer,
+                                          offset=wl_pin.center())
+
             left_pin = self.local_insts[0].get_pin(wl_name)
             right_pin = self.local_insts[-1].get_pin(wl_name)
             self.add_layout_pin_segment_center(text=wl_name,
-                                               layer=left_pin.layer,
+                                               layer=wl_layer,
                                                start=left_pin.lc(),
                                                end=right_pin.rc())
 

compiler/modules/local_bitcell_array.py

@@ -10,6 +10,7 @@ from globals import OPTS
 from sram_factory import factory
 from vector import vector
 import debug
+from tech import layer_properties as layer_props
 
 
 class local_bitcell_array(bitcell_base_array.bitcell_base_array):
@@ -199,18 +200,22 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
 
             wordline_pins = self.wl_array.get_inputs()
 
+            wl_layer = layer_props.global_bitcell_array.wordline_layer
+            wl_pitch = getattr(self, "{}_pitch".format(wl_layer))
+
             for (wl_name, in_pin_name) in zip(wordline_names, wordline_pins):
                 # wl_pin = self.bitcell_array_inst.get_pin(wl_name)
                 in_pin = self.wl_insts[port].get_pin(in_pin_name)
 
                 y_offset = in_pin.cy()
+
                 if port == 0:
-                    y_offset -= 2 * self.m3_pitch
+                    y_offset -= 2 * wl_pitch
                 else:
-                    y_offset += 2 * self.m3_pitch
+                    y_offset += 2 * wl_pitch
 
                 self.add_layout_pin_segment_center(text=wl_name,
-                                                   layer="m3",
+                                                   layer=wl_layer,
                                                    start=vector(self.wl_insts[port].lx(), y_offset),
                                                    end=vector(self.wl_insts[port].lx() + self.wl_array.width, y_offset))