16 Commits

Author	SHA1	Message	Date
Jesse Cirimelli-Low	374562f354	rbc substrate issues	2022-06-16 15:17:07 -07:00
Jesse Cirimelli-Low	98fe4c74a4	colend fixes in progress	2022-06-15 22:34:21 -07:00
mrg	bbfccd1e00	Remove netlist bl/br swaps on flipped cells	2022-05-23 17:16:36 -07:00
Jesse Cirimelli-Low	172d070880	fix bl routing in rba	2022-05-19 21:45:48 -07:00
Jesse Cirimelli-Low	0667a93d53	single port rba passing lvs	2022-03-07 13:45:50 -08:00
Jesse Cirimelli-Low	038acd1568	single port rba lvs progress	2022-03-07 01:20:59 -08:00
Jesse Cirimelli-Low	8d9166a01b	only rba lvs errors is colend body extraction	2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low	cf8c486cea	merge sky130_dummy_array	2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low	de60a1c38a	merge in opc fixes	2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low	468de963f6	remove add_mod in sky130	2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low	8a0450afac	adjust replica col wls	2021-12-22 15:46:03 -08:00
Jesse Cirimelli-Low	8879820af4	replica col lvs fix	2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low	4e5744df50	remove add_mod()	2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low	ddb76c4aff	fix dummy array opc	2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low	8eb6caa248	fix bitcell array opc errors	2021-12-14 22:15:27 -08:00
mrg	fa2232fc11	Initial commit of sky130 config files	2021-10-04 15:16:28 -07:00