OpenRAM/technology/sky130/modules
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00
..
sky130_bitcell.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_bitcell_array.py single port rba lvs progress 2022-03-07 01:20:59 -08:00
sky130_bitcell_base_array.py single port rba lvs progress 2022-03-07 01:20:59 -08:00
sky130_col_cap.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_col_cap_array.py single port rba passing lvs 2022-03-07 13:45:50 -08:00
sky130_corner.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_dummy_array.py single port rba lvs progress 2022-03-07 01:20:59 -08:00
sky130_dummy_bitcell.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_internal.py fix bitcell array opc errors 2021-12-14 22:15:27 -08:00
sky130_replica_bitcell.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_replica_bitcell_array.py single port rba lvs progress 2022-03-07 01:20:59 -08:00
sky130_replica_column.py single port rba passing lvs 2022-03-07 13:45:50 -08:00
sky130_row_cap.py Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
sky130_row_cap_array.py remove add_mod in sky130 2021-12-22 15:51:49 -08:00