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OpenRAM
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4016 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low e4a895ecb0 fix verbosity level 2026-04-30 13:02:03 -07:00
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Jesse Cirimelli-Low ddac4254ec switch from conda to nix for tooling 2026-04-30 12:00:56 -07:00
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low 5077282180 count wordlines from bottom going up 2026-04-28 14:04:42 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low 3e569feebf Merge branch 'dev' into array_gen 2026-04-22 01:38:59 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low b6d98c44d5 singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
Jesse Cirimelli-Low ffcbd51019 technology switching working 2026-03-17 11:44:20 -07:00
Jesse Cirimelli-Low ab33017fe2
Merge pull request #282 from ruhai-lin/stable 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
 2026-03-12 10:47:23 -07:00
rlin50 6d14626a75 Fix address bit ordering in sky130 1rw characterization 2026-02-23 15:32:08 -08:00
Maarten Boersma 7382ea7dda
fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next 2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00
Eren Dogan 855139bc4e Add Makefile target to run broken tests only 2024-01-19 15:15:52 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
Eren Dogan efd43c3191 Merge branch 'dev' into issue_fix 2023-12-06 13:30:22 -08:00
Eren Dogan 7531e38cad Remove unused local variable 2023-12-05 11:18:58 -08:00
Eren Dogan 39a66fcb87 Fix some lint errors 2023-12-05 11:16:22 -08:00
Eren Dogan 6cfb22959c Remove unused imports 2023-12-05 11:08:32 -08:00
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker b9570b8ddf removed gf180 specific code from ptx 2023-11-07 01:01:05 -08:00
SWalker ce1861f342 proper output rom bank output layer 2023-10-31 23:24:21 -07:00
SWalker d161cc55a5 fixed missing broken stamp 2023-10-31 23:24:21 -07:00
SWalker a45e16bff5 re-added rom tests to regression ignore for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 26068fd2e1 more ptx fixes 2023-10-31 23:24:21 -07:00
SWalker b453aa23c2 fix ptx minwidth calculation for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 5378a308c1 updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing 2023-10-31 23:24:21 -07:00
SWalker 1f35855c6d remove old rom test 2023-10-31 23:24:21 -07:00
SWalker 9b99e6c124 bunch of cleanups to core rom classes 2023-10-31 23:24:21 -07:00
SWalker ddba3b3718 move vdd pins around to make routing nice 2023-10-31 23:24:21 -07:00
SWalker 5c22e382b5 add parameter to make routing horizonal vdd rails easier 2023-10-31 23:24:21 -07:00
SWalker 4b3af38727 change min rail to contact spacing for long gf180 contact extend 2023-10-31 23:24:21 -07:00
SWalker 565e3f6814 flatten ptx in extraction and renumber test based on importance 2023-10-31 23:24:21 -07:00
SWalker 3271c5e73c fixing drc on rom bank, mostly spacing tweaks 2023-10-31 23:24:21 -07:00
SWalker 75f7a5847f fixing contact placement for gf180 in rom 2023-10-31 23:24:21 -07:00
Sage Walker b279791762 added control buf test 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00