OpenRAM/compiler
Jesse Cirimelli-Low b6d98c44d5 singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
..
base Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
characterizer checkpoint from tt submission 2026-01-14 12:08:26 -08:00
datasheet Update copyright year 2024-01-03 14:32:44 -08:00
drc Update copyright year 2024-01-03 14:32:44 -08:00
gdsMill Use library imports globally 2022-11-27 13:01:20 -08:00
model_configs Update copyright year 2024-01-03 14:32:44 -08:00
modules singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
router Update copyright year 2024-01-03 14:32:44 -08:00
tests technology switching working 2026-03-17 11:44:20 -07:00
verify Update copyright year 2024-01-03 14:32:44 -08:00
Makefile Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
debug.py Update copyright year 2024-01-03 14:32:44 -08:00
gen_stimulus.py Update copyright year 2024-01-03 14:32:44 -08:00
globals.py technology switching working 2026-03-17 11:44:20 -07:00
model_data_util.py Update copyright year 2024-01-03 14:32:44 -08:00
options.py Update copyright year 2024-01-03 14:32:44 -08:00
rom.py Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
rom_config.py Update copyright year 2024-01-03 14:32:44 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram.py Update copyright year 2024-01-03 14:32:44 -08:00
sram_config.py checkpoint from tt submission 2026-01-14 12:08:26 -08:00
sram_factory.py Update copyright year 2024-01-03 14:32:44 -08:00
view_profile.py Update copyright year 2024-01-03 14:32:44 -08:00