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OpenRAM
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4965 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 28fef79202 make sky130-install now correctly merges with privded cells 2026-05-04 17:32:07 -07:00
Jesse Cirimelli-Low 797664c343 update sky130 cell paths 2026-05-04 17:15:49 -07:00
Jesse Cirimelli-Low c089ff0e78 update git ignore so we can track just our sky130 cells 2026-05-04 17:07:33 -07:00
Jesse Cirimelli-Low 88cf3ae401 use python venv so we can still run make library 2026-05-04 16:56:27 -07:00
Jesse Cirimelli-Low 5bd5293b4e use python venv with nix 2026-05-04 16:39:33 -07:00
Jesse Cirimelli-Low 07b33b3dfd fix ciel repo 2026-05-04 16:25:26 -07:00
Jesse Cirimelli-Low 4e93ba0424 add ciel to nix flake for pdk managementment 2026-05-04 13:01:52 -07:00
Jesse Cirimelli-Low 03c5a58758 add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
Jesse Cirimelli-Low e4a895ecb0 fix verbosity level 2026-04-30 13:02:03 -07:00
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Jesse Cirimelli-Low ddac4254ec switch from conda to nix for tooling 2026-04-30 12:00:56 -07:00
Jesse Cirimelli-Low 2780fda35c all sky130 crba passing 2026-04-28 23:22:40 -07:00
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low 5077282180 count wordlines from bottom going up 2026-04-28 14:04:42 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low 3e569feebf Merge branch 'dev' into array_gen 2026-04-22 01:38:59 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 5fd548582f bump cell lib version for dual port fixes 2026-04-14 15:10:30 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low b6d98c44d5 singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
Jesse Cirimelli-Low ffcbd51019 technology switching working 2026-03-17 11:44:20 -07:00
Jesse Cirimelli-Low ab33017fe2
Merge pull request #282 from ruhai-lin/stable 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
 2026-03-12 10:47:23 -07:00
rlin50 6d14626a75 Fix address bit ordering in sky130 1rw characterization 2026-02-23 15:32:08 -08:00
rlin50 ec28bc6dfd Fix sky130 1rw LVS mismatch by correcting col_cap pin order 2026-02-22 22:11:35 -08:00
Matt Guthaus c99b134deb
Merge pull request #280 from Aurora7913/issue279 
Fix compatibility with numpy>=2.4.0
 2026-01-16 06:24:55 -08:00
Maarten Boersma e32f3164e4
fix typo 2026-01-16 15:05:30 +01:00
Maarten Boersma 7382ea7dda
fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Matt Guthaus ce5595adf1
Merge pull request #275 from vikashpatel24/dev 
Fix for Missing lef_rom_interconnect in tech.py
 2025-10-17 09:46:49 -07:00
Vikash Patel b9bb6898af Fix for Missing lef_rom_interconnect in tech.py 2025-10-17 14:40:03 +05:30
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Matt Guthaus ea15a81443
Merge pull request #270 from hpretl/stable 
Switching from `volare` to `ciel` and bumping the version number
 2025-06-26 13:15:50 -07:00
Harald Pretl 9492349d7a Bump version 2025-06-26 21:21:13 +02:00
Harald Pretl 01686a2005 Switch from `volare` to `ciel` 2025-06-26 21:21:06 +02:00
Matthew Guthaus e63f70da5e Update README by removing slack and email group. Update website. 2025-04-01 10:44:49 -07:00
Jesse Cirimelli-Low 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next 2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
Jesse Cirimelli-Low 8104a42f0e
Update artifact action 2024-11-13 22:45:31 -08:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
mrg 3184e1d0e4 Merge branch 'add-doc' of github.com:FriedrichWu/OpenRAM into dev 2024-11-12 09:47:57 -08:00
FriedrichWu 7ec407314a add documentation 2024-11-11 16:18:45 +01:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
mrg 3f1f58065d Add nand4 leakage to sky130 tech 2024-07-01 10:14:43 -07:00
mole99 0937f86761 Disable check_lvsdrc for gf180mcu 2024-02-03 12:15:11 +01:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
vlsida-bot b6a6f12642 Bump version: 1.2.47 -> 1.2.48 2024-01-21 17:32:32 +00:00
Eren Dogan 306da8a895 Merge branch 'sky130_regress' into dev 2024-01-20 21:05:22 -08:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00