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add fix for cypress sp wls

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This commit is contained in:
Jesse Cirimelli-Low
2026-04-28 17:19:54 -07:00
parent 5077282180
commit 88241ca685
8 changed files with 35 additions and 35 deletions
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compiler/modules/bitcell_base_array.py
+5 -3
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@@ -121,13 +121,15 @@ class bitcell_base_array(design):
def get_all_wordline_names(self, port=None):
""" Return all the wordline names """
temp = []
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
if len(self.all_ports) > 0:
temp.extend(self.get_rbl_wordline_names(0))
if port == None:
temp.extend(self.all_wordline_names)
else:
temp.extend(self.wordline_names[port])
temp.extend(self.get_rbl_wordline_names(0))
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
return temp
compiler/modules/row_cap_array.py
+1 -1
View File
@@ -103,7 +103,7 @@ class row_cap_array(bitcell_base_array):
max_row = self.row_size - 2
for row in range(0, max_row):
for port in self.all_ports:
wl_pin = self.cell_inst[max_row - 1 - row, 0].get_pin(wl_names[port])
wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1),