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OpenRAM
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3857 Commits

Author SHA1 Message Date
Matt Guthaus 6dc42c4125 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-03-05 22:48:51 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 7e67b741f6 Merge branch 'dev' into multiport_characterization 2019-03-04 00:43:03 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus fb7264bae2 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-28 08:44:18 -08:00
Jesse Cirimelli-Low 3802c537e5 added add_db.py to add .db files to datasheets 2019-02-27 22:20:06 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus fa89e11f95 Merge branch 'multiport' into dev 2019-02-25 17:12:24 -08:00
Matt Guthaus c50c190b68 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-25 17:12:12 -08:00
Matt Guthaus f865e66181 Remove git_id file 2019-02-25 16:47:38 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus c79b97eb51 Merge remote-tracking branch 'origin/dev' into multiport 2019-02-25 15:46:39 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus 638afaeb31 Remove duplicate profile stats script 2019-02-25 10:14:02 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Jesse Cirimelli-Low 34294443d4 updated logos and css for official colors 2019-02-25 07:46:34 -08:00
Jesse Cirimelli-Low 677588290d merging with dev now that it is passing 2019-02-25 07:05:06 -08:00
Matt Guthaus 52a02a68de Merge branch 'multiport' of github.com:VLSIDA/PrivateRAM into multiport 2019-02-24 11:05:05 -08:00
Matt Guthaus be741a6828 Fix mising file 2019-02-24 11:04:56 -08:00
Matt Guthaus a210fdda0f Fix arguments for none verification 2019-02-24 10:49:35 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract. 2019-02-24 07:26:21 -08:00
Jesse Cirimelli-Low b9525e0f9e Merge branch 'dev' into datasheet_gen 2019-02-23 15:45:51 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 0cb7c2b090 Add port makeall for removing symmetry problems in netgen 2019-02-22 17:10:23 -08:00
Matt Guthaus 79465cc2e1 Fix extract bug. 2019-02-22 16:44:50 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 27d05e9b36 Remove outdated SRAM layout virtuoso library 2019-02-22 14:51:21 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Jesse Cirimelli-Low 8c9c910855 Merge branch 'datasheet_gen' into dev 2019-02-22 11:41:03 -08:00
Jesse Cirimelli-Low ff09254590 fixed analytical flag 2019-02-22 08:19:54 -08:00
Jesse Cirimelli-Low 0cabee060d fixed area rounding 2019-02-22 06:57:54 -08:00
Jesse Cirimelli-Low b4f1d53a1b fixed DRC datasheet error 2019-02-22 06:46:28 -08:00
Matt Guthaus d043c72277 Fix temp name error in openram.py 2019-02-21 11:16:21 -08:00
Matt Guthaus bb408d0a45 Add missing / in output path for log 2019-02-21 10:23:30 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Matt Guthaus f30743aa7e Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2019-02-17 10:36:58 -08:00
Matt Guthaus 39bcdc8a58 Remove outdated docs. Add Docker info to README.md 2019-02-17 10:35:56 -08:00
Jesse Cirimelli-Low 723ec9925f Merge branch 'datasheet_gen' into dev 2019-02-15 21:47:24 -08:00