Merge branch 'multiport' into dev

compiler/example_configs/example_config_1rw_1r_scn4m_subm.py

@@ -1,8 +1,6 @@
 word_size = 2
 num_words = 16
 
-bitcell = "bitcell_1rw_1r"
-replica_bitcell = "replica_bitcell_1rw_1r"
 num_rw_ports = 1
 num_r_ports = 1
 num_w_ports = 0

compiler/example_configs/example_config_1w_1r_scn4m_subm.py

@@ -1,8 +1,6 @@
 word_size = 2
 num_words = 16
 
-bitcell = "bitcell_1w_1r"
-replica_bitcell = "replica_bitcell_1w_1r"
 num_rw_ports = 1
 num_r_ports = 1
 num_w_ports = 0

compiler/git_id

@@ -1 +0,0 @@
-468eb9a4a038201c2b0004fe6e4ae9b2d37fdd57

compiler/globals.py

@@ -132,6 +132,8 @@ def init_openram(config_file, is_unit_test=True):
 
     from sram_factory import factory
     factory.reset()
+
+    setup_bitcell()
     
     # Reset the static duplicate name checker for unit tests.
     import hierarchy_design
@@ -157,6 +159,42 @@ def init_openram(config_file, is_unit_test=True):
     if not CHECKPOINT_OPTS:
         CHECKPOINT_OPTS = copy.copy(OPTS)
     
+def setup_bitcell():
+    """
+    Determine the correct custom or parameterized bitcell for the design.
+    """
+    global OPTS
+
+    if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
+        OPTS.bitcell = "bitcell"
+        OPTS.replica_bitcell = "replica_bitcell"
+    # If we have non-1rw ports, figure out the right bitcell to use
+    else:
+        ports = ""
+        if OPTS.num_rw_ports>0:
+            ports += "{}rw_".format(OPTS.num_rw_ports)
+        if OPTS.num_w_ports>0:
+            ports += "{}w_".format(OPTS.num_w_ports)
+        if OPTS.num_r_ports>0:
+            ports += "{}r".format(OPTS.num_r_ports)
+
+        OPTS.bitcell = "bitcell_"+ports
+        OPTS.replica_bitcell = "replica_bitcell_"+ports
+
+        # See if a custom bitcell exists
+        from importlib import find_loader
+        bitcell_loader = find_loader(OPTS.bitcell)
+        replica_bitcell_loader = find_loader(OPTS.replica_bitcell)
+        # Use the pbitcell if we couldn't find a custom bitcell
+        # or its custom replica  bitcell
+        if bitcell_loader==None or replica_bitcell_loader==None:
+            # Use the pbitcell (and give a warning if not in unit test mode)
+            OPTS.bitcell = "pbitcell"
+            OPTS.replica_bitcell = "replica_pbitcell"
+            if not OPTS.is_unit_test:
+                debug.warning("Using the parameterized bitcell which may have suboptimal density.")
+        else:
+            debug.info(1,"Using custom bitcell: {}".format(OPTS.bitcell))    
 
 
 def get_tool(tool_type, preferences, default_name=None):
@@ -250,7 +288,8 @@ def read_config(config_file, is_unit_test=True):
                                                          OPTS.num_words,
                                                          ports,
                                                          OPTS.tech_name)
-    
+
+        
 
         
 def end_openram():