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OpenRAM
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551 Commits

Author SHA1 Message Date
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols 3e0a49e58d Added options for the model type in timing graph (cacti or elmore) 2021-07-25 22:28:23 -07:00
Hunter Nichols 5ad86538d4 Renamed graph_util to timing_graph to match the module name 2021-07-25 20:21:54 -07:00
Hunter Nichols 7fc4469b97 Converted input load to Farads for cacti module to fit other units. 2021-07-25 17:22:03 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
mrg 2711093442 Improve signal debug output 2021-07-01 12:47:17 -07:00
mrg bbdc728ac5 Edits to functional simulation. 
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
 2021-07-01 09:59:13 -07:00
Hunter Nichols 8c48520de6 Added cacti-like model and adapted several functions from cacti into python. 2021-06-30 15:50:54 -07:00
mrg 1ae68637ee Utilize same format for output 2021-06-29 17:04:32 -07:00
mrg 91603e7e01 Fix spare+value notation error 2021-06-29 16:44:52 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg 4a9f361ab9 Save raw file by default for Xyce. Change command debug level. 2021-06-29 11:27:33 -07:00
mrg ee1c2054d3 Add formatted debug output 2021-06-29 11:26:49 -07:00
mrg d2a1f6b654 Add num_rows/cols to sim 2021-06-29 09:35:33 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 470317eaa4 Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules. 2021-06-21 17:20:25 -07:00
mrg d53bc98ff5 Exit with error when spice models not found. Use ngspice if no simulator defined. 2021-06-21 13:14:08 -07:00
Hunter Nichols 131ff8bcef Changed the regression test to only run models for the output being tested. 2021-06-16 23:50:20 -07:00
mrg b7f1c8e8fc Fix name for detecting single port 2021-06-16 19:07:56 -07:00
mrg c7c319c11f Use extra bitcell version tag only for single port in sky130 2021-06-16 19:06:12 -07:00
mrg d119a0e7ff Use sky130 bitcell in simulation for BLs 2021-06-16 18:45:53 -07:00
mrg 6ac082ce23 Only replace simulator if it is defined. 2021-06-16 10:44:13 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
Hunter Nichols 3d82718f5a Changed neural network model to be sklearn based 2021-06-07 12:26:45 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
Hunter Nichols b3bcf48d2e Merge branch 'dev' into automated_analytical_model 2021-05-26 18:42:24 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
mrg 4a8e0cdabb Add top-level pin functionality 2021-05-26 15:04:52 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 76f5578cc1 Removed path delays from characterization output to not disturb the current testing flow. 2021-05-25 15:19:27 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
Hunter Nichols 1488b31dce Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well. 2021-05-24 12:53:51 -07:00
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
mrg 9c01e22281 Prioritize Xyce. 2021-05-21 12:05:10 -07:00
mrg f856a44376 Restrict to direct KLU solver 2021-05-21 12:04:26 -07:00
mrg fc17a1ff45 Xyce can be capital or lower case 2021-05-21 12:04:26 -07:00
mrg eadf7eedc5 Prioritize Xyce to last until bugs resolved. 2021-05-21 10:01:37 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00