 Hadir Khan
|
9d6052b86c
|
fix for matching the layout vs verilog port names for rom
|
2023-12-20 15:30:07 -08:00 |
|
 SWalker
|
b9570b8ddf
|
removed gf180 specific code from ptx
|
2023-11-07 01:01:05 -08:00 |
|
|
SWalker
|
ce1861f342
|
proper output rom bank output layer
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
26068fd2e1
|
more ptx fixes
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
b453aa23c2
|
fix ptx minwidth calculation for freepdk45
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
5378a308c1
|
updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
9b99e6c124
|
bunch of cleanups to core rom classes
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
ddba3b3718
|
move vdd pins around to make routing nice
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
5c22e382b5
|
add parameter to make routing horizonal vdd rails easier
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
4b3af38727
|
change min rail to contact spacing for long gf180 contact extend
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
3271c5e73c
|
fixing drc on rom bank, mostly spacing tweaks
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
75f7a5847f
|
fixing contact placement for gf180 in rom
|
2023-10-31 23:24:21 -07:00 |
|
|
SWalker
|
a544abebf7
|
fixed contact area issue
|
2023-10-31 23:24:21 -07:00 |
|
 Sage Walker
|
cb8567c66f
|
spacing tweaks for gf180 address control gate
|
2023-10-31 23:24:21 -07:00 |
|
|
Sage Walker
|
d6cb15c82d
|
Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
|
2023-10-31 23:24:21 -07:00 |
|
|
Sage Walker
|
b0a0226e87
|
rom array compatability changes
|
2023-10-31 23:24:21 -07:00 |
|
 Sam Crow
|
bf49ea744e
|
force multi-delay chain pinouts to be user configurable
|
2023-09-27 13:15:45 -07:00 |
|
 Eren Dogan
|
f8b2c1e9b9
|
Change OPTS.route_supplies option since there's only one router now
|
2023-08-02 21:48:29 -07:00 |
|
|
Eren Dogan
|
54fc34392d
|
Remove unnecessary imports
|
2023-08-02 21:28:21 -07:00 |
|
|
Eren Dogan
|
87eca6b7db
|
Use the initial bbox to route supply and signals
|
2023-08-02 18:01:09 -07:00 |
|
|
Eren Dogan
|
5b0f97860a
|
Calculate bbox inside the router
|
2023-08-02 09:30:50 -07:00 |
|
|
Eren Dogan
|
877f20e071
|
Use the new routers in ROMs
|
2023-08-01 19:10:02 -07:00 |
|
|
Eren Dogan
|
dd152da5c2
|
Change signal escape router's high-level function name
|
2023-08-01 11:26:25 -07:00 |
|
|
Eren Dogan
|
993b47be4c
|
Remove old routers from sram_1bank
|
2023-08-01 11:22:50 -07:00 |
|
|
Eren Dogan
|
db2a276077
|
Split graph router class to use it for signal escaping later
|
2023-07-31 19:43:09 -07:00 |
|
|
Eren Dogan
|
54ce1377c5
|
Merge branch 'dev' into gridless_router
|
2023-07-25 20:03:59 -07:00 |
|
|
Eren Dogan
|
5de7b9cda7
|
Make graph router the default supply router
|
2023-07-24 13:07:43 -07:00 |
|
|
Sam Crow
|
09aa395174
|
cast pins dict to list
|
2023-07-18 16:13:29 -07:00 |
|
|
Eren Dogan
|
53d00f5b34
|
Merge branch 'dev' into gridless_router
|
2023-07-18 10:00:00 -07:00 |
|
|
Eren Dogan
|
5ef964d01f
|
Merge branch 'dev' into gridless_router
|
2023-07-18 09:31:20 -07:00 |
|
|
Eren Dogan
|
094e71764a
|
Change option name for the gridless router
|
2023-07-13 12:16:58 -07:00 |
|
|
Sam Crow
|
b91c628acf
|
Merge branch 'dev' into delay_ctrl
|
2023-07-06 08:45:03 -07:00 |
|
|
Sam Crow
|
468c972acb
|
add optional guard band to delay chain sizing
|
2023-07-05 16:34:42 -07:00 |
|
|
Sam Crow
|
d65ccfcc95
|
fix column mux without rbl start_bit to 0
|
2023-07-05 13:17:46 -07:00 |
|
|
Sam Crow
|
b4a9784835
|
model vth delay swing delay
|
2023-07-05 12:17:48 -07:00 |
|
|
Sam Crow
|
5235cf9667
|
model p_en and wl_en delays in delay chain sizing
|
2023-07-03 17:02:11 -07:00 |
|
|
Sam Crow
|
e1865083d7
|
incomplete work on improved delay modeling
|
2023-06-29 14:44:42 -07:00 |
|
|
Sam Crow
|
28ea93bd0a
|
convert 1-indexing to 0-indexing
|
2023-06-25 11:03:10 -07:00 |
|
|
Sam Crow
|
006eacd6d0
|
add pinout message output
|
2023-06-25 10:46:58 -07:00 |
|
|
Sam Crow
|
8992c0fb68
|
first approximation of delay values
|
2023-06-20 16:22:03 -07:00 |
|
|
Sam Crow
|
dbc9de6c9a
|
implement relationship between delay pinouts
|
2023-06-14 17:10:07 -07:00 |
|
 Gary Mejia
|
9a36cce7ae
|
Fixed formatting on all files
|
2023-06-14 12:28:36 -07:00 |
|
|
Sam Crow
|
bf516a927d
|
add skeleton for delay chain sizing
|
2023-06-13 13:44:32 -07:00 |
|
|
Sam Crow
|
fee90283b9
|
add spacing and a comment
|
2023-06-12 16:56:44 -07:00 |
|
|
Gary Mejia
|
692acd2066
|
Verilog ROM model created for testing
|
2023-06-12 15:35:54 -07:00 |
|
|
Sam Crow
|
ce622952ef
|
route rbl conditionally
|
2023-06-08 12:36:31 -07:00 |
|
|
Sam Crow
|
a51b71d460
|
update copyright
|
2023-06-08 12:36:12 -07:00 |
|
|
samuelkcrow
|
afd3b782b9
|
remove cs_bar signal bus from all control logics
|
2023-06-07 15:53:15 -07:00 |
|
|
samuelkcrow
|
a48842ff72
|
fix code format issues from 00 test
|
2023-06-07 15:52:25 -07:00 |
|
|
samuelkcrow
|
b9492051b6
|
use control_logic_base in control_logic_delay
|
2023-06-07 15:51:19 -07:00 |
|