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__init__.py
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Change rom_base_bank name and top pin names
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2023-03-30 11:30:50 -07:00 |
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and2_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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and3_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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and4_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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bank.py
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Merge branch 'dev' into delay_ctrl
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2023-06-05 16:24:48 -07:00 |
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bitcell_1port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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bitcell_2port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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bitcell_array.py
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2023-01-28 22:56:27 -08:00 |
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bitcell_base.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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bitcell_base_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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capped_replica_bitcell_array.py
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change array modules to allow rbl=[0, 0]
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2023-03-09 10:23:28 -08:00 |
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col_cap_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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col_cap_bitcell_1port.py
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Over-ride build_graph in row/col caps to remove incorrect graph error.
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2023-03-01 09:25:56 -08:00 |
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col_cap_bitcell_2port.py
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Over-ride build_graph in row/col caps to remove incorrect graph error.
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2023-03-01 09:25:56 -08:00 |
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column_decoder.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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column_mux.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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column_mux_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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control_logic.py
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remove cs_bar signal bus from all control logics
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2023-06-07 15:53:15 -07:00 |
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control_logic_base.py
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remove cs_bar signal bus from all control logics
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2023-06-07 15:53:15 -07:00 |
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control_logic_delay.py
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add optional guard band to delay chain sizing
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2023-07-05 16:34:42 -07:00 |
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delay_chain.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dff.py
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2023-01-28 22:56:27 -08:00 |
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dff_array.py
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2023-01-28 22:56:27 -08:00 |
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dff_buf.py
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2023-01-28 22:56:27 -08:00 |
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dff_buf_array.py
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2023-01-28 22:56:27 -08:00 |
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dff_inv.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dff_inv_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dummy_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dummy_bitcell_1port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dummy_bitcell_2port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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dummy_pbitcell.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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global_bitcell_array.py
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add no rbl support to global array
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2023-04-05 14:47:15 -07:00 |
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hierarchical_decoder.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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hierarchical_predecode.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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hierarchical_predecode2x4.py
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2023-01-28 22:56:27 -08:00 |
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hierarchical_predecode3x8.py
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2023-01-28 22:56:27 -08:00 |
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hierarchical_predecode4x16.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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internal_base.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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inv_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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local_bitcell_array.py
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support no rbls in local array
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2023-03-09 14:44:05 -08:00 |
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multi_delay_chain.py
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add pinout message output
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2023-06-25 10:46:58 -07:00 |
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multibank.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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nand2_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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nand3_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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nand4_dec.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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orig_bitcell_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pand2.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pand3.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pand4.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pbitcell.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pbuf.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pbuf_dec.py
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column control and address precharge
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2023-03-30 11:30:50 -07:00 |
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pdriver.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pgate.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pinv.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pinv_dec.py
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Changes for test generation and simulation
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2023-03-30 11:30:50 -07:00 |
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pinvbuf.py
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revert changes to pinvbuf
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2023-03-30 11:30:50 -07:00 |
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pnand2.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pnand3.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pnand4.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pnor2.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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port_address.py
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place wl_en pin on wl drivers in absence of rbl_wl driver
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2023-06-05 15:26:11 -07:00 |
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port_data.py
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fix column mux without rbl start_bit to 0
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2023-07-05 13:17:46 -07:00 |
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precharge.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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precharge_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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ptristate_inv.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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ptx.py
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reoriented cell and added tap cell
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2023-03-30 11:30:50 -07:00 |
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pwrite_driver.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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replica_bitcell_1port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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replica_bitcell_2port.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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replica_bitcell_array.py
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reword comments in replica bitcell array module
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2023-06-06 14:43:18 -07:00 |
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replica_column.py
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Merge remote-tracking branch 'origin/dev' into no_rbl
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2023-02-20 22:11:02 -08:00 |
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replica_pbitcell.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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rom_address_control_array.py
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more top level routing cleanup
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2023-03-30 11:30:50 -07:00 |
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rom_address_control_buf.py
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more code cleaning
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2023-03-30 11:30:50 -07:00 |
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rom_bank.py
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Verilog ROM model created for testing
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2023-06-12 15:35:54 -07:00 |
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rom_base_array.py
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1kb rom DRC clean
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2023-03-30 11:30:50 -07:00 |
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rom_base_cell.py
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precharge array test passing sky130
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2023-03-30 11:30:50 -07:00 |
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rom_column_mux.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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rom_column_mux_array.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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rom_control_logic.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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rom_decoder.py
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more code cleaning
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2023-03-30 11:30:50 -07:00 |
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rom_poly_tap.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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rom_precharge_array.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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rom_precharge_cell.py
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precharge array test passing sky130
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2023-03-30 11:30:50 -07:00 |
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rom_wordline_driver_array.py
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rom base passing tests with top level routing
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2023-03-30 11:30:50 -07:00 |
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row_cap_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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row_cap_bitcell_1port.py
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Over-ride build_graph in row/col caps to remove incorrect graph error.
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2023-03-01 09:25:56 -08:00 |
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row_cap_bitcell_2port.py
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Over-ride build_graph in row/col caps to remove incorrect graph error.
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2023-03-01 09:25:56 -08:00 |
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sense_amp.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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sense_amp_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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sram_1bank.py
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Make graph router the default supply router
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2023-07-24 13:07:43 -07:00 |
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sram_multibank.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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sram_multibank_template.v
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Shrunk address register in multibank verilog
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2022-07-28 15:03:41 -07:00 |
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template.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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tri_gate.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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tri_gate_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wordline_buffer_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wordline_driver.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wordline_driver_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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write_driver.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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write_driver_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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write_mask_and_array.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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