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18,032 Commits 159 Branches 71 Tags
ea4634ecee09e953a85bf957727ee908895596fe
Commit Graph
2176 Commits
Author SHA1 Message Date
Emil J. Tywoniak ea4634ecee twine: remove LeafIdString since it was designed to cope with lack of content hashing 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak 090ac110a8 twine: remove TwineSearch and friends 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak 5721446ea7 twine: content hashing 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak d5decad312 twines: reduce structural loss 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak 7bf2352473 twines: big cleanup 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak 992c8c2eb3 twines: use LeafIdString codebase-wide 2026-10-02 18:42:02 +02:00
Emil J. Tywoniak 080e46417a verific: twines 2026-10-02 18:42:01 +02:00
Emil J. Tywoniak 62fb600000 use twines() for brevity 2026-10-02 18:42:01 +02:00
Emil J. Tywoniak 6f0e648543 twine: split Twine into in-memory TwineNode that doesn't support autoidx variants and temporary TwineSpec that does 2026-10-02 18:42:01 +02:00
Emil J. Tywoniak 7d4d4833b2 frontends: use twine suffix nodes for hierarchical names, cache name lookups 2026-10-02 18:42:01 +02:00
Emil J. Tywoniak fa45832fbc frontends: trivial twine damage 2026-10-02 18:42:01 +02:00
Emil J. Tywoniak 6bd1badfbd kernel: reimplement IdString as handle on a Twine in a per-design TwinePool 2026-10-02 18:34:52 +02:00
Emil J 2750a02e0c Merge pull request #6264 from YosysHQ/emil/read_verilog-array-signedness 
read_verilog: fix sign extension in array pattern assignments
 2026-10-01 13:56:38 +00:00
Emil J cd7af6bcb6 Merge pull request #6263 from YosysHQ/emil/abc_new-unmapped-error-handling 
abc_new: improve error handling of &get
 2026-09-30 14:11:56 +00:00
Emil J. Tywoniak c783ccfdd6 read_verilog: fix sign extension in array pattern assignments 2026-09-30 12:59:01 +02:00
Emil J. Tywoniak 4c391fdf5b read_xaiger: skip symbol table instead of crashing since its handling was removed 2026-09-30 11:43:00 +02:00
Miodrag Milanovic ef887f64f6 Update sv-elab and slang to v12.0 2026-09-29 18:09:25 +02:00
Miodrag Milanović 303b1ff528 Merge pull request #6204 from YosysHQ/mmicko/logger 
logger: add LogSourceLocation
 2026-09-23 10:48:18 +00:00
Miodrag Milanovic 6557982d0a logger: make log_verific_callback simple 2026-09-22 13:15:32 +02:00
nella 315f8194a0 Don't mark cells w no unput as boxes. 2026-09-21 16:58:03 +02:00
nella d8d54fafd7 Mark cells as imported correctly. 2026-09-21 16:57:58 +02:00
Emil J 150c32b03e Merge pull request #6154 from YosysHQ/emil/liberty-filter 
liberty: add filtering for things we need
 2026-09-16 16:44:09 +00:00
Miodrag Milanovic b8bfd05a93 logger: few more cleanups 2026-09-16 13:10:26 +02:00
Miodrag Milanovic 7149b19f64 read_verilog logging to_src() - > to_loc() 2026-09-16 12:30:40 +02:00
Miodrag Milanovic 32ef29fafb logger: added non-fatal errors and update verific logging 2026-09-16 09:24:46 +02:00
Miodrag Milanovic 18239a6fbb logger: add LogSourceLocation 2026-09-15 14:29:36 +02:00
Emil J. Tywoniak 5c6c0f66e3 abc: re-isolate autoidx churn 2026-09-10 18:16:57 +02:00
Emil J. Tywoniak 2a1c20dbbe liberty: add filtering for things we need 2026-09-10 16:12:49 +02:00
Miodrag Milanović 87b17517fd Merge pull request #6188 from YosysHQ/revert-6182-lofty/revert-read_xaiger2 
Revert "Temporarily revert #6101 and #6077"
 2026-09-10 09:17:02 +00:00
Miodrag Milanovic ec25ee4de8 Fix remaining mentions, and update links 2026-09-10 10:24:34 +02:00
Gus Smith 697fed66da Rename SymbiYosys to SBY 2026-09-10 10:08:49 +02:00
Miodrag Milanović ae86bbb130 Revert "Temporarily revert #6101 and #6077" 2026-09-10 09:09:13 +02:00
Emil J 5274c96506 Merge pull request #6161 from YosysHQ/emil/remove-dead-bindings 
rtlil: remove dead verilog bindings
 2026-09-09 16:51:35 +00:00
Miodrag Milanovic a80623137a sv-elab: Update to release 2026-09-08 2026-09-08 11:58:13 +02:00
Lofty 51583d854a Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8" 
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
 2026-09-07 17:29:08 +01:00
Lofty c53d452134 Revert "Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10" 
This reverts commit 621d943ac8, reversing
changes made to 598862f45b.
 2026-09-04 11:16:11 +01:00
Miodrag Milanović 28b7a17675 Merge pull request #6115 from YosysHQ/log-sink 
log rewrite [sc-748]
 2026-09-02 13:03:29 +00:00
Miodrag Milanovic 7c10ee1c58 Update sv-elab as of 2026-09-01 2026-09-01 08:20:05 +02:00
Emil J. Tywoniak fbd7c249ec rtlil: remove dead verilog bindings 2026-08-31 22:13:01 +02:00
Miodrag Milanovic 726aff678f log: remove log_ prefix and unified some namings 2026-08-31 11:20:21 +02:00
Emil J e3af33003d Merge pull request #6141 from john-kearney/fix-json-netnames-signed 
json: read 'signed' on netnames, matching ports
 2026-08-24 10:19:44 +00:00
Emil J 85acd07685 Merge pull request #6123 from sifferman/fix-resetall-default-nettype 
Fix resetall not affecting default_nettype
 2026-08-24 09:47:04 +00:00
tangxifan 02dc5a82d7 [core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration 
[core] debug yosys version extraction

[core] debug

[core] now cache the cmake source dir

[core] debug

[core] debug kernel dependencies

[core] debug common include directories

[core] debug

[core] debug simlib_help.inc

[core] debug pmgen py path in cmake

[core] syntax

[core] debug flex source

[core] restore

[core] debug executable output as it now shows linking to .

[core] debug yosys-abc directory

[core] debug cmake share directory

[core] debug yosys abc

[core] restore shared directory location as yosys requires fixed location

[core] rework link target to yosys sub dir under build

[core] fixed the bug on yosys-config.install location for install

[core] cmake syntax

[core] correct the location for share directory

[core] debug

[core] debug

[core] debug

[core] enforce internal attributes; rename the YOSYS_ENABLE_UNIT_TESTS; use YOSYS_CMAKE_BINARY_DIR for all

[core] apply review comments

[core] rename

[core] change all the CMAKE_BINARY_DIR to YOSYS_CMAKE_BINARY_DIR

[core] replace CMAKE_SOURCE_DIR to YOSYS_CMAKE_SOURCE_DIR
 2026-08-21 12:09:04 -07:00
John Kearney 0f5efca3c9 json: read 'signed' attribute on netnames, matching ports 
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.

Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
 2026-08-20 22:20:24 -07:00
Miodrag Milanovic caad7779e0 log: propagate format information 2026-08-20 17:30:44 +02:00
Miodrag Milanovic 2e113f5eff log: create LogManager singleton and move implementation 2026-08-19 15:59:46 +02:00
Lofty 621d943ac8 Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10 
read_xaiger2: remove
 2026-08-17 17:42:25 +00:00
Ethan Sifferman 4bd6be5b0f reset default_nettype on `resetall for the lexer 2026-08-16 14:26:21 -07:00
Miodrag Milanovic cbbd8c0dfd log: convert all to sinks 2026-08-14 11:55:46 +02:00
nella b8959e70ba Merge pull request #6072 from YosysHQ/nella/dlatchlibmap-cleanup 
Update to `dfflibmap` to be able to map LATCHes (clean up of #5976)
 2026-08-13 08:38:19 +00:00