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frontends: use twine suffix nodes for hierarchical names, cache name lookups

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:01 +02:00
parent fa45832fbc
commit 7d4d4833b2
8 changed files with 428 additions and 257 deletions
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frontends/aiger/aigerparse.cc
+62 -40
View File
@@ -211,6 +211,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString
: design(design), f(f), clk_name(clk_name), map_filename(map_filename), aiger_autoidx(autoidx++)
{
module = new RTLIL::Module;
module->design = design;
module->name = module_name;
if (design->module(module->name))
log_error("Duplicate definition of module %s!\n", module->name.unescape());
@@ -260,13 +261,14 @@ end_of_header:
else
log_abort();
RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
RTLIL::Wire* n0 = aiger_wires.count(0) ? aiger_wires.at(0) : nullptr;
if (n0)
module->connect(n0, State::S0);
// Parse footer (symbol table, comments, etc.)
unsigned l1;
std::string s;
TwineSearch search(&design->twines);
for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
f.ignore(1);
@@ -276,7 +278,7 @@ end_of_header:
if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
log_error("Line %u has invalid symbol position!\n", line_count);
RTLIL::IdString escaped_s = stringf("\\%s", s);
std::string escaped_s = stringf("\\%s", s);
RTLIL::Wire* wire;
if (c == 'i') {
log_assert(l1 < inputs.size());
@@ -285,7 +287,7 @@ end_of_header:
log_assert(l1 < latches.size());
wire = latches[l1];
} else if (c == 'o') {
wire = module->wire(escaped_s);
wire = module->wire(search.find(escaped_s));
log_assert(l1 < outputs.size());
if (wire) {
// Could have been renamed by a latch
@@ -298,7 +300,7 @@ end_of_header:
wire = bad_properties[l1];
} else log_abort();
module->rename(wire, escaped_s);
module->rename(wire, intern_name(escaped_s, search));
}
else if (c == 'j' || c == 'f') {
// TODO
@@ -337,25 +339,41 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned
{
const unsigned variable = literal >> 1;
const bool invert = literal & 1;
RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
RTLIL::Wire *wire = module->wire(wire_name);
if (wire) return wire;
if (auto it = aiger_wires.find(literal); it != aiger_wires.end())
return it->second;
std::string wire_name = stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : "");
RTLIL::Wire *wire = module->wire(design->twines.find(wire_name));
if (wire) {
aiger_wires[literal] = wire;
return wire;
}
log_debug2("Creating %s\n", wire_name.c_str());
wire = module->addWire(wire_name);
wire->port_input = wire->port_output = false;
aiger_wires[literal] = wire;
if (!invert) return wire;
RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
if (wire_inv) {
if (module->cell(wire_inv_name)) return wire;
const unsigned base_literal = variable << 1;
RTLIL::Wire *wire_inv;
bool wire_inv_existed = true;
if (auto it = aiger_wires.find(base_literal); it != aiger_wires.end()) {
wire_inv = it->second;
}
else {
log_debug2("Creating %s\n", wire_inv_name.c_str());
wire_inv = module->addWire(wire_inv_name);
wire_inv->port_input = wire_inv->port_output = false;
std::string wire_inv_name = stringf("$aiger%d$%d", aiger_autoidx, variable);
wire_inv = module->wire(design->twines.find(wire_inv_name));
if (!wire_inv) {
wire_inv_existed = false;
log_debug2("Creating %s\n", wire_inv_name);
wire_inv = module->addWire(std::move(wire_inv_name));
wire_inv->port_input = wire_inv->port_output = false;
}
aiger_wires[base_literal] = wire_inv;
}
log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
if (wire_inv_existed && module->cell(wire_inv->name))
return wire;
log_debug2("Creating %s = ~$aiger%d$%d\n", wire_name.c_str(), aiger_autoidx, variable);
module->addNotGate(stringf("$not$aiger%d$%d", aiger_autoidx, variable), wire_inv, wire);
return wire;
@@ -396,7 +414,7 @@ void AigerReader::parse_xaiger()
else
log_abort();
RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
RTLIL::Wire* n0 = aiger_wires.count(0) ? aiger_wires.at(0) : nullptr;
if (n0)
module->connect(n0, State::S0);
@@ -425,7 +443,7 @@ void AigerReader::parse_xaiger()
uint32_t rootNodeID = parse_xaiger_literal(f);
uint32_t cutLeavesM = parse_xaiger_literal(f);
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
RTLIL::Wire *output_sig = aiger_wires.at(rootNodeID << 1);
log_assert(output_sig);
uint32_t nodeID;
RTLIL::SigSpec input_sig;
@@ -436,7 +454,7 @@ void AigerReader::parse_xaiger()
log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
continue;
}
RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
RTLIL::Wire *wire = aiger_wires.at(nodeID << 1);
log_assert(wire);
input_sig.append(wire);
}
@@ -455,7 +473,7 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr);
lut_mask.set(gray, o.data);
}
RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
RTLIL::Cell *output_cell = module->cell(design->twines.find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
log_assert(output_cell);
module->remove(output_cell);
module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::move(lut_mask));
@@ -482,14 +500,14 @@ void AigerReader::parse_xaiger()
std::getline(f, outPinName, '\0');
uint32_t inPinNum = parse_xaiger_literal(f);
log_debug2("M: cellID=%u cellName=%s outPinName=%s inPinNum=%u\n", i, cellName, outPinName, inPinNum);
mapping_cell.type = RTLIL::escape_id(cellName);
mapping_cell.out = RTLIL::escape_id(outPinName);
mapping_cell.type = design->twines.add(std::string{RTLIL::escape_id(cellName)});
mapping_cell.out = design->twines.add(std::string{RTLIL::escape_id(outPinName)});
for (unsigned j = 0; j < inPinNum; ++j) {
auto inPinName = std::string{};
std::getline(f, inPinName, '\0');
log_debug2("M: inPinName=%s\n", inPinName);
mapping_cell.ins.push_back(RTLIL::escape_id(inPinName));
mapping_cell.ins.push_back(design->twines.add(std::string{RTLIL::escape_id(inPinName)}));
}
if (!design->module(mapping_cell.type)) {
@@ -512,19 +530,19 @@ void AigerReader::parse_xaiger()
log_assert(cellID < cellNum);
MappingCell &mapping_cell = mapping_cells.at(cellID);
log_debug2("M: instanceID=%u cellID=%u outPort=%s rootNodeID=%u\n", i, cellID, RTLIL::unescape_id(mapping_cell.out), rootNodeID);
log_debug2("M: instanceID=%u cellID=%u outPort=%s rootNodeID=%u\n", i, cellID, design->twines.unescaped_str(mapping_cell.out).c_str(), rootNodeID);
RTLIL::Wire *output_sig = createWireIfNotExists(module, rootNodeID);
log_assert(output_sig);
{
RTLIL::IdString output_cell_name;
std::string output_cell_name;
if ((rootNodeID & 1) == 0) { // uninverted
output_cell_name = stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID >> 1);
} else { // inverted
output_cell_name = stringf("$not$aiger%d$%d", aiger_autoidx, rootNodeID >> 1);
}
RTLIL::Cell *output_cell = module->cell(output_cell_name);
RTLIL::Cell *output_cell = module->cell(design->twines.find(output_cell_name));
log_assert(output_cell);
module->remove(output_cell);
}
@@ -535,7 +553,7 @@ void AigerReader::parse_xaiger()
for (unsigned j = 0; j < mapping_cell.ins.size(); ++j) {
auto nodeID = parse_xaiger_literal(f);
log_debug("M: inPort=%s nodeID=%u\n", RTLIL::unescape_id(mapping_cell.ins.at(j)), nodeID);
log_debug("M: inPort=%s nodeID=%u\n", design->twines.unescaped_str(mapping_cell.ins.at(j)).c_str(), nodeID);
RTLIL::Wire *input_sig = createWireIfNotExists(module, nodeID);
cell->setPort(mapping_cell.ins.at(j), input_sig);
}
@@ -583,9 +601,10 @@ void AigerReader::parse_xaiger()
uint32_t boxUniqueId = parse_xaiger_literal(f);
log_assert(boxUniqueId > 0);
uint32_t oldBoxNum = parse_xaiger_literal(f);
RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
cell->setPort(ID(i), SigSpec(State::S0, boxInputs));
cell->setPort(ID(o), SigSpec(State::S0, boxOutputs));
IdString _type = module->design->twines.add(std::string{stringf("$__boxid%u", boxUniqueId)});
RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), _type);
cell->setPort(ID::i, SigSpec(State::S0, boxInputs));
cell->setPort(ID::o, SigSpec(State::S0, boxOutputs));
cell->attributes[ID::abc9_box_seq] = oldBoxNum;
boxes.emplace_back(cell);
}
@@ -846,6 +865,16 @@ void AigerReader::parse_aiger_binary()
}
}
IdString AigerReader::intern_name(const std::string &escaped, TwineSearch &search)
{
IdString existing = search.find(escaped);
if (existing != IdString::Null)
return existing;
IdString ref = design->twines.add(std::string{escaped});
search.insert(ref);
return ref;
}
void AigerReader::post_process()
{
unsigned ci_count = 0, co_count = 0;
@@ -888,15 +917,8 @@ void AigerReader::post_process()
design->scratchpad_set_int("read_aiger.co_count", co_count);
// Insert into a new (temporary) design so that "clean" will only
// operate (and run checks on) this one module
RTLIL::Design *mapped_design = new RTLIL::Design;
mapped_design->add(module);
Pass::call(mapped_design, "clean");
mapped_design->modules_.erase(module->name);
delete mapped_design;
design->add(module);
Pass::call_on_module(design, module, "clean");
for (auto cell : module->cells().to_vector()) {
if (cell->type != ID($lut)) continue;
@@ -945,11 +967,11 @@ struct AigerFrontend : public Frontend {
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-module_name" && argidx+1 < args.size()) {
module_name = RTLIL::escape_id(args[++argidx]);
module_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (arg == "-clk_name" && argidx+1 < args.size()) {
clk_name = RTLIL::escape_id(args[++argidx]);
clk_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
@@ -973,7 +995,7 @@ struct AigerFrontend : public Frontend {
free(bn);
#else
char* bn = strdup(filename.c_str());
module_name = RTLIL::escape_id(bn);
module_name = design->twines.add(RTLIL::escape_id(bn));
free(bn);
#endif
}
frontends/aiger/aigerparse.h
+2
View File
@@ -45,6 +45,7 @@ struct AigerReader
std::vector<RTLIL::Wire*> bad_properties;
std::vector<RTLIL::Cell*> boxes;
std::vector<int> mergeability, initial_state;
dict<unsigned, RTLIL::Wire*> aiger_wires;
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename);
void parse_aiger();
@@ -53,6 +54,7 @@ struct AigerReader
void parse_aiger_binary();
void post_process();
IdString intern_name(const std::string &escaped, TwineSearch &search);
RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal);
};
frontends/ast/ast.cc
+96 -40
View File
@@ -43,6 +43,12 @@ namespace AST {
unsigned long long astnode_count() { return astnodes; }
}
TwinePool &AST::ast_name_pool()
{
static TwinePool pool;
return pool;
}
// instantiate global variables (private API)
namespace AST_INTERNAL {
bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
@@ -193,7 +199,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
auto& attr = attributes.at(id);
if (attr->type != AST_CONSTANT)
attr->input_error("Attribute `%s' with non-constant value!\n", id);
attr->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(id));
return attr->integer != 0;
}
@@ -393,7 +399,7 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, "\n");
for (auto &it : attributes) {
fprintf(f, "%s ATTR %s:\n", indent.c_str(), it.first.c_str());
fprintf(f, "%s ATTR %s:\n", indent.c_str(), attr_name_str(it.first).c_str());
it.second->dumpAst(f, indent + " ");
}
@@ -436,7 +442,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
}
for (auto &it : attributes) {
fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(attr_name_str(it.first)).c_str());
it.second->dumpVlog(f, "");
fprintf(f, " *)%s", indent.empty() ? "" : "\n");
}
@@ -1105,6 +1111,22 @@ std::string AstNode::loc_string() const
return stringf("%s:%d.%d-%d.%d", location.begin.filename->c_str(), location.begin.line, location.begin.column, location.end.line, location.end.column);
}
static IdString build_hier_content(TwinePool &pool, std::string_view content)
{
size_t dot = content.rfind('.');
if (dot == std::string_view::npos)
return pool.add(std::string{content}).tag(true);
IdString prefix = build_hier_content(pool, content.substr(0, dot));
return pool.add(Twine::Suffix{prefix, std::string{content.substr(dot)}});
}
IdString AST::intern_hier_name(RTLIL::Design *design, std::string_view escaped)
{
if (escaped.size() > 1 && escaped[0] == '\\')
return build_hier_content(design->twines, escaped.substr(1));
return design->twines.add(std::string{escaped});
}
void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
{
obj->attributes[ID::src] = ast->loc_string();
@@ -1131,9 +1153,10 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
AstModule *module = new AstModule;
current_module = module;
module->design = design;
module->ast = nullptr;
module->name = ast->str;
module->name = design->twines.add(std::string{ast->str});
set_src_attr(module, ast);
module->set_bool_attribute(ID::cells_not_processed);
@@ -1272,8 +1295,8 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
for (auto &attr : ast->attributes) {
log_assert((bool)attr.second.get());
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
module->attributes[attr.first] = attr.second->asAttrConst();
ast->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
module->attributes[design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
for (size_t i = 0; i < ast->children.size(); i++) {
const auto& node = ast->children[i];
@@ -1301,11 +1324,11 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
continue;
module->attributes[attr.first] = attr.second->asAttrConst();
module->attributes[design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
for (const auto& node : ast->children)
if (node->type == AST_PARAMETER)
current_module->avail_parameters(node->str);
current_module->avail_parameters(design->twines.add(std::string(node->str)));
}
if (ast->type == AST_INTERFACE)
@@ -1457,8 +1480,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (defer_local)
child->str = "$abstract" + child->str;
if (design->has(child->str)) {
RTLIL::Module *existing_mod = design->module(child->str);
IdString mod_name = design->twines.find(child->str);
if (design->has(mod_name)) {
RTLIL::Module *existing_mod = design->module(mod_name);
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error(child->location.to_loc(), "Re-definition of module `%s'!\n", child->str);
} else if (nooverwrite) {
@@ -1573,14 +1597,19 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
// that it should be reprocessed once the specified module has been elaborated.
bool AstModule::reprocess_if_necessary(RTLIL::Design *design)
{
std::optional<TwineSearch> search;
for (const RTLIL::Cell *cell : cells())
{
std::string modname = cell->get_string_attribute(ID::reprocess_after);
if (modname.empty())
continue;
if (design->module(modname) || design->module("$abstract" + modname)) {
if (!search)
search.emplace(&design->twines);
IdString mod_ref = search->find(modname);
IdString abstract_ref = search->find("$abstract" + modname);
if (design->module(mod_ref) || design->module(abstract_ref)) {
log("Reprocessing module %s because instantiated module %s has become available.\n",
name.unescape(), RTLIL::unescape_id(modname));
PooledName(design, name).unescape(), RTLIL::unescape_id(modname));
loadconfig();
process_and_replace_module(design, this, ast.get(), NULL);
return true;
@@ -1598,7 +1627,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
auto new_ast = ast->clone();
auto loc = ast->location;
for (auto &intf : local_interfaces) {
std::string intfname = intf.first.str();
std::string intfname = design->twines.str(intf.first);
RTLIL::Module *intfmodule = intf.second;
for (auto w : intfmodule->wires()){
auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
@@ -1626,7 +1655,8 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
std::string interface_type = res.first;
std::string interface_modport = res.second; // Is "", if no modport
if (design->module(interface_type) != nullptr) {
IdString interface_type_ref = design->twines.find(interface_type);
if (design->module(interface_type_ref) != nullptr) {
// Add a cell to the module corresponding to the interface port such that
// it can further propagated down if needed:
auto celltype_for_intf = std::make_unique<AstNode>(loc, AST_CELLTYPE);
@@ -1636,7 +1666,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
new_ast->children.push_back(std::move(cell_for_intf));
// Get all members of this non-overridden dummy interface instance:
RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming
RTLIL::Module *intfmodule = design->module(interface_type_ref); // All interfaces should at this point in time (assuming
// reprocess_module is called from the hierarchy pass) be
// present in design->modules_
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
@@ -1683,10 +1713,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
if (has_interfaces)
new_modname += "$interfaces$" + interf_info;
if (!design->has(new_modname)) {
IdString new_modname_ref = design->twines.find(new_modname);
if (!design->has(new_modname_ref)) {
if (!new_ast) {
auto mod = dynamic_cast<AstModule*>(design->module(modname));
IdString modname_ref = design->twines.find(modname);
auto mod = dynamic_cast<AstModule*>(design->module(modname_ref));
new_ast = mod->ast->clone();
}
modname = new_modname;
@@ -1695,11 +1726,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
// Iterate over all interfaces which are ports in this module:
for(auto &intf : interfaces) {
RTLIL::Module * intfmodule = intf.second;
std::string intfname = intf.first.str();
std::string intfname = design->twines.str(intf.first);
// Check if a modport applies for the interface port:
AstNode *modport = NULL;
if (modports.count(intfname) > 0) {
std::string interface_modport = modports.at(intfname).str();
if (modports.count(intf.first) > 0) {
std::string interface_modport = design->twines.str(modports.at(intf.first));
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
AstNode *ast_node_of_interface = ast_module_of_interface->ast.get();
modport = find_modport(ast_node_of_interface, interface_modport);
@@ -1709,20 +1740,22 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
}
process_module(design, new_ast.get(), false);
design->module(modname)->check();
IdString new_ref = design->twines.find(modname);
design->module(new_ref)->check();
RTLIL::Module* mod = design->module(modname);
RTLIL::Module* mod = design->module(new_ref);
// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
for(auto &intf : interfaces) {
if(mod->wire(intf.first) != nullptr) {
IdString intf_name = intf.first;
if(mod->wire(intf_name) != nullptr) {
// Normally, removing wires would be batched together as it's an
// expensive operation, however, in this case doing so would mean
// that a cell with the same name cannot be created (below)...
// Since we won't expect many interfaces to exist in a module,
// we can let this slide...
pool<RTLIL::Wire*> to_remove;
to_remove.insert(mod->wire(intf.first));
to_remove.insert(mod->wire(intf_name));
mod->remove(to_remove);
mod->fixup_ports();
// We copy the cell of the interface to the sub-module such that it
@@ -1731,7 +1764,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
new_subcell->set_bool_attribute(ID::is_interface);
}
else {
log_error("No port with matching name found (%s) in %s. Stopping\n", intf.first, modname);
log_error("No port with matching name found (%s) in %s. Stopping\n", mod->design->twines.str(intf.first).c_str(), modname);
}
}
@@ -1745,7 +1778,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
return design->twines.add(std::string{modname});
}
// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
@@ -1756,15 +1789,16 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
std::unique_ptr<AstNode> new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast, quiet);
if (!design->has(modname) && new_ast) {
IdString modname_ref = design->twines.add(std::string{modname});
if (!design->has(modname_ref) && new_ast) {
new_ast->str = modname;
process_module(design, new_ast.get(), false, NULL, quiet);
design->module(modname)->check();
design->module(modname_ref)->check();
} else if (!quiet) {
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
return modname_ref;
}
static std::string serialize_param_value(const RTLIL::Const &val) {
@@ -1784,7 +1818,7 @@ static std::string serialize_param_value(const RTLIL::Const &val) {
return res;
}
std::string AST::derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters) {
std::string AST::derived_module_name(std::string stripped_name, const std::vector<std::pair<std::string, RTLIL::Const>> &parameters) {
std::string para_info;
for (const auto &elem : parameters)
para_info += stringf("%s=%s", elem.first, serialize_param_value(elem.second));
@@ -1805,19 +1839,19 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
stripped_name = stripped_name.substr(9);
int para_counter = 0;
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
std::vector<std::pair<std::string, RTLIL::Const>> named_parameters;
for (const auto& child : ast->children) {
if (child->type != AST_PARAMETER)
continue;
para_counter++;
auto it = parameters.find(child->str);
auto it = parameters.find(design->twines.find(child->str));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str, log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
it = parameters.find(stringf("$%d", para_counter));
it = parameters.find(design->twines.find(stringf("$%d", para_counter)));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
@@ -1830,7 +1864,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (parameters.size()) // not named_parameters to cover hierarchical defparams
modname = derived_module_name(stripped_name, named_parameters);
if (design->has(modname))
if (design->has(design->twines.find(modname)))
return modname;
if (!quiet)
@@ -1850,13 +1884,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (child->type != AST_PARAMETER)
continue;
para_counter++;
auto it = parameters.find(child->str);
auto it = parameters.find(design->twines.find(child->str));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str, log_signal(it->second));
goto rewrite_parameter;
}
it = parameters.find(stringf("$%d", para_counter));
it = parameters.find(design->twines.find(stringf("$%d", para_counter)));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
@@ -1881,7 +1915,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (rewritten.count(param.first))
continue;
auto defparam = std::make_unique<AstNode>(loc, AST_DEFPARAM, std::make_unique<AstNode>(loc, AST_IDENTIFIER));
defparam->children[0]->str = param.first.str();
defparam->children[0]->str = design->twines.str(param.first);
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
defparam->children.push_back(AstNode::mkconst_str(loc, param.second.decode_string()));
else
@@ -1897,9 +1931,33 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
RTLIL::Module *AstModule::clone() const
{
AstModule *new_mod = new AstModule;
new_mod->design = design;
new_mod->name = name;
cloneInto(new_mod);
copy_config_into(new_mod);
return new_mod;
}
RTLIL::Module *AstModule::clone(RTLIL::Design *dst) const
{
return clone(dst, dst->twines.copy_from(design->twines, name));
}
RTLIL::Module *AstModule::clone(RTLIL::Design *dst, IdString target_name) const
{
AstModule *new_mod = new AstModule;
new_mod->design = dst;
new_mod->name = target_name;
cloneInto(new_mod);
dst->add(new_mod);
copy_config_into(new_mod);
return new_mod;
}
void AstModule::copy_config_into(AstModule *new_mod) const
{
new_mod->ast = ast->clone();
new_mod->nolatches = nolatches;
new_mod->nomeminit = nomeminit;
@@ -1912,8 +1970,6 @@ RTLIL::Module *AstModule::clone() const
new_mod->icells = icells;
new_mod->pwires = pwires;
new_mod->autowire = autowire;
return new_mod;
}
void AstModule::loadconfig() const
frontends/ast/ast.h
+18 -4
View File
@@ -36,6 +36,10 @@ YOSYS_NAMESPACE_BEGIN
namespace AST
{
TwinePool &ast_name_pool();
inline IdString intern_attr_name(const std::string &name) { return ast_name_pool().add(std::string(name)); }
inline std::string attr_name_str(IdString id) { return ast_name_pool().str(id); }
// all node types, type2str() must be extended
// whenever a new node type is added here
enum AstNodeType
@@ -182,9 +186,10 @@ namespace AST
// the list of child nodes for this node
std::vector<std::unique_ptr<AstNode>> children;
// the list of attributes assigned to this node
std::map<RTLIL::IdString, std::unique_ptr<AstNode>> attributes;
bool get_bool_attribute(RTLIL::IdString id);
// The list of attributes assigned to this node. Keys are IdStrings
std::map<IdString, std::unique_ptr<AstNode>> attributes;
bool get_bool_attribute(IdString id);
bool get_bool_attribute(const std::string &id) { return get_bool_attribute(intern_attr_name(id)); }
// node content - most of it is unused in most node types
std::string str;
@@ -357,6 +362,10 @@ namespace AST
node->set_in_param_flag(true);
attributes[key] = std::move(node);
}
void set_attribute(const std::string &key, std::unique_ptr<AstNode> node)
{
set_attribute(intern_attr_name(key), std::move(node));
}
// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag
// can be overridden based on the intrinsic properties of this node, i.e. based on its type)
@@ -398,6 +407,9 @@ namespace AST
void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
bool reprocess_if_necessary(RTLIL::Design *design) override;
RTLIL::Module *clone() const override;
RTLIL::Module *clone(RTLIL::Design *dst) const override;
RTLIL::Module *clone(RTLIL::Design *dst, IdString target_name) const override;
void copy_config_into(AstModule *new_mod) const;
void loadconfig() const;
};
@@ -423,12 +435,14 @@ namespace AST
AstNode * find_modport(AstNode *intf, std::string name);
void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
IdString intern_hier_name(RTLIL::Design *design, std::string_view escaped);
// Helper for setting the src attribute.
void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);
// generate standard $paramod... derived module name; parameters should be
// in the order they are declared in the instantiated module
std::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);
std::string derived_module_name(std::string stripped_name, const std::vector<std::pair<std::string, RTLIL::Const>> &parameters);
// used to provide simplify() access to the current design for looking up
// modules, ports, wires, etc.
frontends/ast/genrtlil.cc
+90 -83
View File
@@ -27,6 +27,7 @@
*/
#include "kernel/log.h"
#include "kernel/twine.h"
#include "kernel/utils.h"
#include "libs/sha1/sha1.h"
#include "ast.h"
@@ -43,19 +44,19 @@ using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations
static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
IdString name = current_module->design->twines.add(stringf("%s$%s:%d$%d", current_module->design->twines.str(type).c_str(), RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++));
RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
RTLIL::Wire *wire = current_module->addWire(Twine::Suffix{cell->name, "_Y"}, result_width);
set_src_attr(wire, that);
wire->is_signed = that->is_signed;
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
that->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
@@ -75,7 +76,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
return;
}
IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
IdString name = current_module->design->twines.add(stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++));
RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
set_src_attr(cell, that);
@@ -86,8 +87,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
if (that != nullptr)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
that->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
@@ -102,18 +103,18 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
// helper function for creating RTLIL code for binary operations
static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
IdString name = current_module->design->twines.add(stringf("%s$%s:%d$%d", current_module->design->twines.str(type).c_str(), RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++));
RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
RTLIL::Wire *wire = current_module->addWire(Twine::Suffix{cell->name, "_Y"}, result_width);
set_src_attr(wire, that);
wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
that->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
@@ -147,8 +148,8 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
that->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
@@ -161,7 +162,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
return wire;
}
static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
static void check_unique_id(RTLIL::Module *module, const std::string &id,
const AstNode *node, const char *to_add_kind)
{
auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) {
@@ -173,20 +174,21 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
to_add_kind, id.c_str(), existing_kind, location_str.c_str());
};
if (const RTLIL::Wire *wire = module->wire(id))
IdString id_tw = intern_hier_name(module->design, id);
if (const RTLIL::Wire *wire = module->wire(id_tw))
already_exists(wire, "signal");
if (const RTLIL::Cell *cell = module->cell(id))
if (const RTLIL::Cell *cell = module->cell(id_tw))
already_exists(cell, "cell");
if (module->processes.count(id))
already_exists(module->processes.at(id), "process");
if (module->memories.count(id))
already_exists(module->memories.at(id), "memory");
if (module->processes.count(id_tw))
already_exists(module->processes.at(id_tw), "process");
if (module->memories.count(id_tw))
already_exists(module->memories.at(id_tw), "memory");
}
// helper class for rewriting simple lookahead references in AST always blocks
struct AST_INTERNAL::LookaheadRewriter
{
dict<IdString, pair<AstNode*, AstNode*>> lookaheadids;
dict<std::string, pair<AstNode*, AstNode*>> lookaheadids;
void collect_lookaheadids(AstNode *node)
{
@@ -353,8 +355,8 @@ struct AST_INTERNAL::ProcessGenerator
set_src_attr(proc, always.get());
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
always->input_error("Attribute `%s' with non-constant value!\n", attr.first);
proc->attributes[attr.first] = attr.second->asAttrConst();
always->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
proc->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
current_case = &proc->root_case;
@@ -446,7 +448,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::SigSpec lhs = init_lvalue_c;
RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
remove_unwanted_lvalue_bits(lhs, rhs);
sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
sync->actions.push_back({lhs, rhs});
offset += lhs.size();
}
}
@@ -484,10 +486,10 @@ struct AST_INTERNAL::ProcessGenerator
std::string wire_name;
do {
wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
chunk.wire->name, chunk.width+chunk.offset-1, chunk.offset);;
if (chunk.wire->name.str().find('$') != std::string::npos)
wire_name += stringf("$%d", autoidx++);
} while (current_module->wires_.count(wire_name) > 0);
} while (current_module->wire(current_module->design->twines.find(wire_name)) != nullptr);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
set_src_attr(wire, always.get());
@@ -662,7 +664,7 @@ struct AST_INTERNAL::ProcessGenerator
current_case_assigned_bits.insert(bit);
remove_unwanted_lvalue_bits(lvalue, rvalue);
current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
current_case->actions.push_back({lvalue, rvalue});
}
break;
@@ -679,8 +681,8 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
sw->attributes[attr.first] = attr.second->asAttrConst();
ast->input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
sw->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
RTLIL::SigSpec this_case_eq_lvalue;
@@ -800,8 +802,8 @@ struct AST_INTERNAL::ProcessGenerator
Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
set_src_attr(en, ast);
proc->root_case.actions.push_back(SigSig(en, false));
current_case->actions.push_back(SigSig(en, true));
proc->root_case.actions.push_back({en, SigSpec(false)});
current_case->actions.push_back({en, SigSpec(true)});
RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder;
@@ -884,7 +886,7 @@ struct AST_INTERNAL::ProcessGenerator
if (ast->type == AST_FAIR) { flavor = "fair"; desc = "assume (eventually)"; }
if (ast->type == AST_COVER) { flavor = "cover"; desc = "cover ()"; }
IdString cellname;
std::string cellname;
if (ast->str.empty())
cellname = stringf("$%s$%s:%d$%d", flavor, RTLIL::encode_filename(*ast->location.begin.filename), ast->location.begin.line, autoidx++);
else
@@ -895,10 +897,10 @@ struct AST_INTERNAL::ProcessGenerator
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_ID, check);
Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
Wire *en = current_module->addWire(cellname + "_EN", 1);
set_src_attr(en, ast);
proc->root_case.actions.push_back(SigSig(en, false));
current_case->actions.push_back(SigSig(en, true));
proc->root_case.actions.push_back({en, SigSpec(false)});
current_case->actions.push_back({en, SigSpec(true)});
RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder;
@@ -918,7 +920,7 @@ struct AST_INTERNAL::ProcessGenerator
cell->set_bool_attribute(ID(keep));
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(ast->location.to_loc(), "Attribute `%s' with non-constant value!\n", attr.first);
log_file_error(ast->location.to_loc(), "Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[attr.first] = attr.second->asAttrConst();
}
cell->setParam(ID::FLAVOR, flavor);
@@ -959,9 +961,10 @@ struct AST_INTERNAL::ProcessGenerator
int cur_idx = GetSize(sync->mem_write_actions);
RTLIL::MemWriteAction action;
set_src_attr(&action, child.get());
action.memid = memid;
action.memid = current_module->design->twines.add(std::string(memid));
action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid]->width, true, &subst_rvalue_map.stdmap());
IdString memid_tw = current_module->design->twines.find(memid);
action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid_tw]->width, true, &subst_rvalue_map.stdmap());
action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst();
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
@@ -1392,9 +1395,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
// This is used by the hierarchy pass to know when it can replace interface connection with the individual
// signals.
RTLIL::IdString id = str;
const std::string &id = str;
check_unique_id(current_module, id, this, "interface port");
RTLIL::Wire *wire = current_module->addWire(id, 1);
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id), 1);
set_src_attr(wire, this);
wire->start_offset = 0;
wire->port_id = port_id;
@@ -1420,9 +1423,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// remember the parameter, needed for example in techmap
case AST_PARAMETER:
current_module->avail_parameters(str);
current_module->avail_parameters(current_module->design->twines.add(std::string(str)));
if (GetSize(children) >= 1 && children[0]->type == AST_CONSTANT) {
current_module->parameter_default_values[str] = children[0]->asParaConst();
current_module->parameter_default_values[current_module->design->twines.add(std::string(str))] = children[0]->asParaConst();
}
YS_FALLTHROUGH
case AST_LOCALPARAM:
@@ -1432,9 +1435,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
input_error("Parameter `%s' with non-constant value!\n", str);
RTLIL::Const val = children[0]->bitsAsConst();
RTLIL::IdString id = str;
const std::string &id = str;
check_unique_id(current_module, id, this, "pwire");
RTLIL::Wire *wire = current_module->addWire(id, GetSize(val));
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id), GetSize(val));
current_module->connect(wire, val);
wire->is_signed = children[0]->is_signed;
@@ -1443,8 +1446,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
wire->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
}
break;
@@ -1457,9 +1460,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (!(range_left + 1 >= range_right))
input_error("Signal `%s' with invalid width range %d!\n", str, range_left - range_right + 1);
RTLIL::IdString id = str;
const std::string &id = str;
check_unique_id(current_module, id, this, "signal");
RTLIL::Wire *wire = current_module->addWire(id, range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(intern_hier_name(current_module->design, id), range_left - range_right + 1);
set_src_attr(wire, this);
wire->start_offset = range_right;
wire->port_id = port_id;
@@ -1471,8 +1474,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
wire->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
if (is_wand) wire->set_bool_attribute(ID::wand);
@@ -1489,9 +1492,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (!children[0]->range_valid || !children[1]->range_valid)
input_error("Memory `%s' with non-constant width or size!\n", str);
RTLIL::Memory *memory = new RTLIL::Memory;
check_unique_id(current_module, str, this, "memory");
RTLIL::Memory *memory = current_module->addMemory(intern_hier_name(current_module->design, str));
set_src_attr(memory, this);
memory->name = str;
memory->width = children[0]->range_left - children[0]->range_right + 1;
if (children[1]->range_right < children[1]->range_left) {
memory->start_offset = children[1]->range_right;
@@ -1500,13 +1503,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
memory->start_offset = children[1]->range_left;
memory->size = children[1]->range_right - children[1]->range_left + 1;
}
check_unique_id(current_module, memory->name, this, "memory");
current_module->memories[memory->name] = memory;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first);
memory->attributes[attr.first] = attr.second->asAttrConst();
input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
memory->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
}
break;
@@ -1547,10 +1548,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(id2ast != nullptr);
if (id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
RTLIL::Wire *wire = current_module->addWire(str);
IdString str_ref = intern_hier_name(current_module->design, str);
if (id2ast->type == AST_AUTOWIRE && current_module->wire(str_ref) == nullptr) {
RTLIL::Wire *wire = current_module->addWire(str_ref);
str_ref = wire->name;
set_src_attr(wire, this);
wire->name = str;
if (flag_autowire)
log_file_warning(location.to_loc(), "Identifier `%s' is implicitly declared.\n", str);
@@ -1563,8 +1566,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk = RTLIL::Const(id2ast->children[0]->bits);
goto use_const_chunk;
}
else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
RTLIL::Wire *current_wire = current_module->wire(str);
else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wire(str_ref) != nullptr) {
RTLIL::Wire *current_wire = current_module->wire(str_ref);
if (current_wire->get_bool_attribute(ID::is_interface))
is_interface = true;
// Ignore
@@ -1584,7 +1587,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
// with the individual signals:
if (is_interface) {
IdString dummy_wire_name = stringf("$dummywireforinterface%s", str);
IdString dummy_wire_name = current_module->design->twines.add(stringf("$dummywireforinterface%s", str));
RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name);
if (!dummy_wire) {
dummy_wire = current_module->addWire(dummy_wire_name);
@@ -1593,7 +1596,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return dummy_wire;
}
wire = current_module->wires_[str];
wire = current_module->wire(str_ref);
chunk.wire = wire;
chunk.width = wire->width;
chunk.offset = 0;
@@ -1960,7 +1963,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
set_src_attr(cell, this);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
IdString mem_tw = current_module->design->twines.find(str);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[mem_tw]->width);
set_src_attr(wire, this);
int mem_width, mem_size, addr_bits;
@@ -2010,13 +2014,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
SigSpec addr_sig = children[0]->genRTLIL();
IdString mem_tw = current_module->design->twines.find(str);
cell->setPort(ID::ADDR, addr_sig);
cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[mem_tw]->width * num_words, true));
cell->setPort(ID::EN, en_sig);
cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[mem_tw]->width);
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}
@@ -2036,7 +2041,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (type == AST_FAIR) { flavor = "fair"; desc = "assume property (eventually)"; }
if (type == AST_COVER) { flavor = "cover"; desc = "cover property ()"; }
IdString cellname;
std::string cellname;
if (str.empty())
cellname = stringf("$%s$%s:%d$%d", flavor, RTLIL::encode_filename(*location.begin.filename), location.begin.line, autoidx++);
else
@@ -2051,8 +2056,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
set_src_attr(cell, this);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
input_error("Attribute `%s' with non-constant value!\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
cell->setParam(ID(FLAVOR), flavor);
cell->parameters[ID::TRG_WIDTH] = 0;
@@ -2097,28 +2102,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
{
int port_counter = 0, para_counter = 0;
RTLIL::IdString id = str;
const std::string &id = str;
check_unique_id(current_module, id, this, "cell");
RTLIL::Cell *cell = current_module->addCell(id, "");
RTLIL::Cell *cell = current_module->addCell(intern_hier_name(current_module->design, id), IdString::Null);
set_src_attr(cell, this);
for (auto it = children.begin(); it != children.end(); it++) {
auto* child = it->get();
if (child->type == AST_CELLTYPE) {
cell->type = child->str;
if (flag_icells && cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
std::string type_str = child->str;
if (flag_icells && type_str.size() >= 2 && type_str[0] == '\\' && type_str[1] == '$')
type_str = type_str.substr(1);
cell->type = current_module->design->twines.add(std::string{type_str});
continue;
}
if (child->type == AST_PARASET) {
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
IdString paraname = current_module->design->twines.add(child->str.empty() ? stringf("$%d", ++para_counter) : child->str);
const auto* value = child->children[0].get();
if (value->type == AST_REALVALUE)
log_file_warning(location.to_loc(), "Replacing floating point parameter %s.%s = %f with string.\n",
cell, paraname.unescape(), value->realvalue);
cell, PooledName(current_module->design, paraname).unescape(), value->realvalue);
else if (value->type != AST_CONSTANT)
input_error("Parameter %s.%s with non-constant value!\n",
cell, paraname.unescape());
cell, PooledName(current_module->design, paraname).unescape());
cell->parameters[paraname] = value->asParaConst();
continue;
}
@@ -2145,7 +2151,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} else if (arg->is_signed) {
// non-trivial signed nodes are indirected through
// signed wires to enable sign extension
RTLIL::IdString wire_name = NEW_ID;
IdString wire_name = current_module->design->twines.add(NEW_ID);
RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig));
wire->is_signed = true;
current_module->connect(wire, sig);
@@ -2155,9 +2161,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (child->str.size() == 0) {
char buf[100];
snprintf(buf, 100, "$%d", ++port_counter);
cell->setPort(buf, sig);
cell->setPort(current_module->design->twines.add(std::string{std::string(buf)}), sig);
} else {
cell->setPort(child->str, sig);
cell->setPort(current_module->design->twines.add(std::string{child->str}), sig);
}
continue;
}
@@ -2170,8 +2176,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value.\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
input_error("Attribute `%s' with non-constant value.\n", attr_name_str(attr.first));
cell->attributes[current_module->design->twines.add(attr_name_str(attr.first))] = attr.second->asAttrConst();
}
if (cell->type == ID($specify2)) {
int src_width = GetSize(cell->getPort(ID::SRC));
@@ -2262,7 +2268,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (width <= 0)
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
Cell *cell = current_module->addCell(myid, str.substr(1));
IdString _type = current_module->design->twines.add(std::string{str.substr(1)});
Cell *cell = current_module->addCell(myid, _type);
set_src_attr(cell, this);
cell->parameters[ID::WIDTH] = width;
frontends/ast/simplify.cc
+42 -15
View File
@@ -693,17 +693,32 @@ static std::string prefix_id(const std::string &prefix, const std::string &str)
// direct access to this global should be limited to the following two functions
static const RTLIL::Design *simplify_design_context = nullptr;
static dict<std::string, RTLIL::IdString> simplify_design_modules;
static size_t simplify_design_modules_size = 0;
void AST::set_simplify_design_context(const RTLIL::Design *design)
{
log_assert(!simplify_design_context || !design);
simplify_design_context = design;
simplify_design_modules.clear();
simplify_design_modules_size = 0;
}
// lookup the module with the given name in the current design context
static const RTLIL::Module* lookup_module(const std::string &name)
{
return simplify_design_context->module(name);
const RTLIL::Design *design = simplify_design_context;
if (const RTLIL::Module *module = design->module(design->twines.find(name)))
return module;
if (simplify_design_modules_size != design->modules_.size()) {
simplify_design_modules.clear();
for (const auto &it : design->modules_)
simplify_design_modules[design->twines.str(it.first)] = it.first;
simplify_design_modules_size = design->modules_.size();
}
auto it = simplify_design_modules.find(name);
return it == simplify_design_modules.end() ? nullptr : design->module(it->second);
}
const RTLIL::Module* AstNode::lookup_cell_module()
@@ -741,7 +756,8 @@ const RTLIL::Module* AstNode::lookup_cell_module()
if (child->str.empty() && para_counter >= module->avail_parameters.size())
return nullptr; // let hierarchy handle this error
IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++] : child->str;
IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++]
: module->design->twines.add(std::string(child->str));
const AstNode *value = child->children[0].get();
if (value->type != AST_REALVALUE && value->type != AST_CONSTANT)
@@ -750,11 +766,11 @@ const RTLIL::Module* AstNode::lookup_cell_module()
}
// put the parameters in order and generate the derived module name
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
std::vector<std::pair<std::string, RTLIL::Const>> named_parameters;
for (RTLIL::IdString param : module->avail_parameters) {
auto it = cell_params_map.find(param);
if (it != cell_params_map.end())
named_parameters.emplace_back(it->first, it->second);
named_parameters.emplace_back(module->design->twines.str(it->first), it->second);
}
std::string modname = celltype->str;
if (cell_params_map.size()) // not named_parameters to cover hierarchical defparams
@@ -951,8 +967,9 @@ static void check_auto_nosync(AstNode *node)
{
std::vector<RTLIL::IdString> attrs_to_drop;
for (const auto& elem : node->attributes) {
std::string attr_str = attr_name_str(elem.first);
// skip attributes that don't begin with the prefix
if (elem.first.compare(0, auto_nosync_prefix.size(),
if (attr_str.compare(0, auto_nosync_prefix.size(),
auto_nosync_prefix.c_str()))
continue;
@@ -960,7 +977,7 @@ static void check_auto_nosync(AstNode *node)
attrs_to_drop.push_back(elem.first);
// find the wire based on the attribute
std::string wire_name = elem.first.substr(auto_nosync_prefix.size());
std::string wire_name = attr_str.substr(auto_nosync_prefix.size());
auto it = current_scope.find(wire_name);
if (it == current_scope.end())
continue;
@@ -977,8 +994,8 @@ static void check_auto_nosync(AstNode *node)
}
// remove the attributes we've "consumed"
for (RTLIL::IdString str : attrs_to_drop) {
auto it = node->attributes.find(str);
for (IdString id : attrs_to_drop) {
auto it = node->attributes.find(id);
node->attributes.erase(it);
}
@@ -1473,14 +1490,20 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
module = lookup_cell_module();
if (module) {
size_t port_counter = 0;
dict<std::string, IdString> ports_by_name;
for (auto port : module->ports)
ports_by_name[module->design->twines.str(port)] = port;
for (auto& child : children) {
if (child->type != AST_ARGUMENT)
continue;
// determine the full name of port this argument is connected to
RTLIL::IdString port_name;
if (child->str.size())
port_name = child->str;
if (child->str.size()) {
auto it = ports_by_name.find(child->str);
if (it != ports_by_name.end())
port_name = it->second;
}
else {
if (port_counter >= module->ports.size())
input_error("Cell instance has more ports than the module!\n");
@@ -1491,7 +1514,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
const RTLIL::Wire *ref = module->wire(port_name);
if (ref == nullptr)
input_error("Cell instance refers to port %s which does not exist in module %s!.\n",
port_name.unescape(), module->name.unescape());
child->str.size() ? RTLIL::unescape_id(child->str)
: module->design->twines.unescaped_str(port_name),
module->name.unescape());
// select the argument, if present
log_assert(child->children.size() <= 1);
@@ -1516,7 +1541,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
// create the indirection wire
std::stringstream sstr;
sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
sstr << "$indirect$" << ref->name.str() << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
std::string tmp_str = sstr.str();
add_wire_for_ref(location, ref, tmp_str);
@@ -4376,13 +4401,15 @@ skip_dynamic_range_lvalue_expansion:;
cell->str = prefix.substr(0, GetSize(prefix)-1);
cell->children[0]->str = celltype;
for (auto& attr : decl->attributes)
if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)
for (auto& attr : decl->attributes) {
std::string attr_str = attr_name_str(attr.first);
if (attr_str.rfind("\\via_celltype_defparam_", 0) == 0)
{
auto cell_arg = std::make_unique<AstNode>(location, AST_PARASET, attr.second->clone());
cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));
cell_arg->str = RTLIL::escape_id(attr_str.substr(strlen("\\via_celltype_defparam_")));
cell->children.push_back(std::move(cell_arg));
}
}
for (auto& child : decl->children)
if (child->type == AST_WIRE && (child->is_input || child->is_output || (type == AST_FCALL && child->str == str)))
frontends/rpc/rpc_frontend.cc
+18 -18
View File
@@ -115,7 +115,7 @@ struct RpcServer {
return modules;
}
std::pair<std::string, std::string> derive_module(const std::string &module, const dict<RTLIL::IdString, RTLIL::Const> &parameters) {
std::pair<std::string, std::string> derive_module(const RTLIL::Design *design, const std::string &module, const dict<IdString, RTLIL::Const> &parameters) {
Json::object json_parameters;
for (auto &param : parameters) {
std::string type, value;
@@ -130,7 +130,7 @@ struct RpcServer {
value = param.second.as_string();
} else
log_cmd_error("Unserializable constant flags 0x%x\n", param.second.flags);
json_parameters[param.first.str()] = Json::object {
json_parameters[design->twines.str(param.first)] = Json::object {
{ "type", type },
{ "value", value },
};
@@ -167,8 +167,8 @@ struct RpcModule : RTLIL::Module {
std::string parameter_info;
for (auto &param : parameters) {
log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second)));
parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second)));
log("Parameter %s = %s\n", PooledName(design, param.first).unescape(), log_signal(RTLIL::SigSpec(param.second)));
parameter_info += stringf("%s=%s", PooledName(design, param.first).unescape(), log_signal(RTLIL::SigSpec(param.second)));
}
std::string derived_name;
@@ -179,11 +179,12 @@ struct RpcModule : RTLIL::Module {
else
derived_name = "$paramod" + stripped_name + parameter_info;
if (design->has(derived_name)) {
IdString derived_ref = design->twines.find(derived_name);
if (design->has(derived_ref)) {
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
} else {
std::string command, input;
std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters);
std::tie(command, input) = server->derive_module(design, stripped_name.substr(1), parameters);
std::istringstream input_stream(input);
RTLIL::Design *derived_design = new RTLIL::Design;
@@ -207,26 +208,24 @@ struct RpcModule : RTLIL::Module {
for (auto module : derived_design->modules())
for (auto cell : module->cells())
if (name_mangling.count(cell->type.str()))
cell->type = name_mangling[cell->type.str()];
cell->type = cell->module->design->twines.add(name_mangling[cell->type.str()]);
for (auto module : derived_design->modules_) {
std::string mangled_name = name_mangling[module.first.str()];
std::string mangled_name = name_mangling[derived_design->twines.str(module.first)];
log("Importing `%s' as `%s'.\n", module.first.unescape(), mangled_name);
log("Importing `%s' as `%s'.\n", PooledName(derived_design, module.first).unescape(), mangled_name);
module.second->name = mangled_name;
module.second->design = design;
module.second->attributes.erase(ID::top);
if (!module.second->has_attribute(ID::hdlname))
module.second->set_string_attribute(ID::hdlname, module.first.str());
design->modules_[mangled_name] = module.second;
derived_design->modules_.erase(module.first);
IdString original_name = module.first;
RTLIL::Module *t = module.second->clone(design, design->twines.add(mangled_name));
t->attributes.erase(ID::top);
if (!t->has_attribute(ID::hdlname))
t->set_string_attribute(ID::hdlname, derived_design->twines.str(original_name));
}
delete derived_design;
}
return derived_name;
return design->twines.add(derived_name);
}
RTLIL::Module *clone() const override {
@@ -588,7 +587,8 @@ cleanup_path:
for (auto &module_name : server->get_module_names()) {
log("Linking module `%s'.\n", module_name);
RpcModule *module = new RpcModule;
module->name = "$abstract\\" + module_name;
module->design = design;
module->name = design->twines.add("$abstract\\" + module_name);
module->server = server;
design->add(module);
}
frontends/rtlil/rtlil_frontend.cc
+100 -57
View File
@@ -23,7 +23,9 @@
#include "kernel/register.h"
#include "kernel/log.h"
#include "kernel/rtlil.h"
#include "kernel/utils.h"
#include "kernel/twine.h"
#include <charconv>
#include <deque>
#include <optional>
@@ -48,6 +50,19 @@ struct RTLILFrontendWorker {
std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
std::vector<RTLIL::CaseRule*> case_stack;
dict<size_t, IdString> twine_remap;
std::vector<IdString> twine_parser_holds;
struct TwineDesc {
enum Kind { Leaf, Suffix } kind;
std::string text;
size_t parent = 0;
bool materializing = false;
};
dict<size_t, TwineDesc> twine_descs;
template <typename... Args>
[[noreturn]]
void error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
@@ -158,7 +173,7 @@ struct RTLILFrontendWorker {
error("Expected EOL, got `%s'.", error_token());
}
std::optional<RTLIL::IdString> try_parse_id()
std::optional<std::string> try_parse_id()
{
char ch = line[0];
if (ch != '\\' && ch != '$')
@@ -170,15 +185,15 @@ struct RTLILFrontendWorker {
break;
++idx;
}
IdString result(line.substr(0, idx));
std::string result(line.substr(0, idx));
line = line.substr(idx);
consume_whitespace_and_comments();
return result;
}
RTLIL::IdString parse_id()
std::string parse_id()
{
std::optional<RTLIL::IdString> id = try_parse_id();
std::optional<std::string> id = try_parse_id();
if (!id.has_value())
error("Expected ID, got `%s'.", error_token());
return std::move(*id);
@@ -328,7 +343,7 @@ struct RTLILFrontendWorker {
error("No wires found for legalization");
int hash = hash_ops<RTLIL::IdString>::hash(id).yield();
RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size));
log("Legalizing wire `%s' to `%s'.\n", id.unescape(), wire->name.unescape());
log("Legalizing wire `%s' to `%s'.\n", PooledName(current_module->design, id).unescape(), wire->name.unescape());
return wire;
}
@@ -342,18 +357,34 @@ struct RTLILFrontendWorker {
parts.push_back(parse_sigspec());
for (auto it = parts.rbegin(); it != parts.rend(); ++it)
sig.append(std::move(*it));
} else if (std::optional<IdString> handle = try_parse_twine_handle()) {
IdString ref = *handle;
RTLIL::Wire *wire = current_module->wire(ref);
if (wire == nullptr) {
if (flag_legalize)
wire = legalize_wire(ref);
else
error("Wire %s not found.", design->twines.str(ref).c_str());
}
sig = RTLIL::SigSpec(wire);
} else {
// We could add a special path for parsing IdStrings that must already exist,
// as here.
// We don't need to addref/release in this case.
std::optional<RTLIL::IdString> id = try_parse_id();
std::optional<std::string> id = try_parse_id();
if (id.has_value()) {
RTLIL::Wire *wire = current_module->wire(*id);
const std::string &s = *id;
bool pub = !s.empty() && s[0] == '\\';
IdString ref = (design->twines.find(pub ? s.substr(1) : s)).tag(pub);
RTLIL::Wire *wire = current_module->wire(ref);
if (wire == nullptr) {
if (flag_legalize)
wire = legalize_wire(*id);
else
wire = legalize_wire(design->twines.add(std::string(*id)));
else {
for (auto wire : current_module->wires())
design->twines.dump(wire->name);
error("Wire `%s' not found.", *id);
}
}
sig = RTLIL::SigSpec(wire);
} else {
@@ -410,22 +441,22 @@ struct RTLILFrontendWorker {
void parse_module()
{
RTLIL::IdString module_name = parse_id();
IdString module_name = parse_twine();
expect_eol();
bool delete_current_module = false;
if (design->has(module_name)) {
RTLIL::Module *existing_mod = design->module(module_name);
if (!flag_overwrite && (flag_lib || (attrbuf.count(ID::blackbox) && attrbuf.at(ID::blackbox).as_bool()))) {
log("Ignoring blackbox re-definition of module %s.\n", module_name);
log("Ignoring blackbox re-definition of module %s.\n", design->twines.str(module_name).c_str());
delete_current_module = true;
} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
error("RTLIL error: redefinition of module %s.", module_name);
error("RTLIL error: redefinition of module %s.", design->twines.str(module_name).c_str());
} else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", module_name);
log("Ignoring re-definition of module %s.\n", design->twines.str(module_name).c_str());
delete_current_module = true;
} else {
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", module_name);
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", design->twines.str(module_name).c_str());
design->remove(existing_mod);
}
}
@@ -485,7 +516,7 @@ struct RTLILFrontendWorker {
void parse_attribute()
{
RTLIL::IdString id = parse_id();
IdString id = parse_twine();
RTLIL::Const c = parse_const();
attrbuf.insert({std::move(id), std::move(c)});
expect_eol();
@@ -623,7 +654,7 @@ struct RTLILFrontendWorker {
void parse_parameter()
{
RTLIL::IdString id = parse_id();
IdString id = parse_twine();
current_module->avail_parameters(id);
if (try_parse_eol())
return;
@@ -645,17 +676,18 @@ struct RTLILFrontendWorker {
while (true)
{
std::optional<RTLIL::IdString> id = try_parse_id();
if (id.has_value()) {
if (current_module->wire(*id) != nullptr) {
if (flag_legalize) {
log("Legalizing redefinition of wire %s.\n", *id);
pool<RTLIL::Wire*> wires = {current_module->wire(*id)};
std::optional<IdString> name = try_parse_twine();
if (name) {
IdString wire_name = *name;
if (current_module->wire(wire_name) != nullptr) {
if (flag_legalize) {
log("Legalizing redefinition of wire %s.\n", design->twines.str(wire_name).c_str());
pool<RTLIL::Wire*> wires = {current_module->wire(wire_name)};
current_module->remove(wires);
} else
error("RTLIL error: redefinition of wire %s.", *id);
error("RTLIL error: redefinition of wire %s.", design->twines.str(wire_name).c_str());
}
wire = current_module->addWire(std::move(*id));
wire = current_module->addWire(wire_name);
break;
}
if (try_parse_keyword("width")){
@@ -709,18 +741,20 @@ struct RTLILFrontendWorker {
int width = 1;
int start_offset = 0;
int size = 0;
IdString mem_name = IdString::Null;
while (true)
{
std::optional<RTLIL::IdString> id = try_parse_id();
if (id.has_value()) {
if (current_module->memories.count(*id) != 0) {
std::optional<IdString> name = try_parse_twine();
if (name.has_value()) {
mem_name = *name;
if (current_module->memories.count(mem_name) != 0) {
if (flag_legalize) {
log("Legalizing redefinition of memory %s.\n", *id);
current_module->remove(current_module->memories.at(*id));
log("Legalizing redefinition of memory %s.\n", design->twines.str(mem_name).c_str());
current_module->remove(current_module->memories.at(mem_name));
} else
error("RTLIL error: redefinition of memory %s.", *id);
error("RTLIL error: redefinition of memory %s.", design->twines.str(mem_name).c_str());
}
memory->name = std::move(*id);
memory->name = mem_name;
break;
}
if (try_parse_keyword("width")){
@@ -749,41 +783,43 @@ struct RTLILFrontendWorker {
memory->width = width;
memory->start_offset = start_offset;
memory->size = size;
current_module->memories.insert({memory->name, memory});
memory->module = current_module;
current_module->memories.insert({mem_name, memory});
expect_eol();
}
void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name)
{
std::string width_param_name = port_name.str() + "_WIDTH";
if (cell->parameters.count(width_param_name) == 0)
IdString width_param = design->twines.find(design->twines.str(port_name) + "_WIDTH");
if (width_param == IdString::Null || cell->parameters.count(width_param) == 0)
return;
RTLIL::Const &param = cell->parameters.at(width_param_name);
RTLIL::Const &param = cell->parameters.at(width_param);
if (param.as_int() != 0)
return;
cell->parameters[width_param_name] = RTLIL::Const(cell->getPort(port_name).size());
cell->parameters[width_param] = RTLIL::Const(cell->getPort(port_name).size());
}
void parse_cell()
{
RTLIL::IdString cell_type = parse_id();
RTLIL::IdString cell_name = parse_id();
IdString cell_type_ref = parse_twine();
IdString cell_name_ref = parse_twine();
expect_eol();
if (current_module->cell(cell_name) != nullptr) {
if (current_module->cell(cell_name_ref) != nullptr) {
if (flag_legalize) {
RTLIL::IdString new_name;
std::string base = design->twines.str(cell_name_ref);
std::string new_name_str;
int suffix = 1;
do {
new_name = RTLIL::IdString(cell_name.str() + "_" + std::to_string(suffix));
new_name_str = base + "_" + std::to_string(suffix);
cell_name_ref = design->twines.add(std::string(new_name_str));
++suffix;
} while (current_module->cell(new_name) != nullptr);
log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name, new_name);
cell_name = new_name;
} while (current_module->cell(cell_name_ref) != nullptr);
log("Legalizing redefinition of cell %s by renaming to %s.\n", base.c_str(), new_name_str.c_str());
} else
error("RTLIL error: redefinition of cell %s.", cell_name);
error("RTLIL error: redefinition of cell %s.", design->twines.str(cell_name_ref).c_str());
}
RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type);
RTLIL::Cell *cell = current_module->addCell(cell_name_ref, cell_type_ref);
cell->attributes = std::move(attrbuf);
while (true)
@@ -799,7 +835,7 @@ struct RTLILFrontendWorker {
} else if (try_parse_keyword("unsized")) {
is_unsized = true;
}
RTLIL::IdString param_name = parse_id();
IdString param_name = parse_twine();
RTLIL::Const val = parse_const();
if (is_signed)
val.flags |= RTLIL::CONST_FLAG_SIGNED;
@@ -810,14 +846,14 @@ struct RTLILFrontendWorker {
cell->parameters.insert({std::move(param_name), std::move(val)});
expect_eol();
} else if (try_parse_keyword("connect")) {
RTLIL::IdString port_name = parse_id();
IdString port_name = parse_twine();
if (cell->hasPort(port_name)) {
if (flag_legalize)
log("Legalizing redefinition of cell port %s.", port_name);
log("Legalizing redefinition of cell port %s.", design->twines.str(port_name).c_str());
else
error("RTLIL error: redefinition of cell port %s.", port_name);
error("RTLIL error: redefinition of cell port %s.", design->twines.str(port_name).c_str());
}
cell->setPort(std::move(port_name), parse_sigspec());
cell->setPort(port_name, parse_sigspec());
if (flag_legalize)
legalize_width_parameter(cell, port_name);
expect_eol();
@@ -863,7 +899,7 @@ struct RTLILFrontendWorker {
"The assign statement is reordered to come before all switch statements.");
RTLIL::SigSpec s1 = parse_sigspec();
RTLIL::SigSpec s2 = parse_sigspec();
current_case->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
current_case->actions.push_back({std::move(s1), std::move(s2)});
expect_eol();
} else
return;
@@ -914,15 +950,15 @@ struct RTLILFrontendWorker {
void parse_process()
{
RTLIL::IdString proc_name = parse_id();
IdString proc_name = parse_twine();
expect_eol();
if (current_module->processes.count(proc_name) != 0) {
if (flag_legalize) {
log("Legalizing redefinition of process %s.\n", proc_name);
log("Legalizing redefinition of process %s.\n", design->twines.str(proc_name).c_str());
current_module->remove(current_module->processes.at(proc_name));
} else
error("RTLIL error: redefinition of process %s.", proc_name);
error("RTLIL error: redefinition of process %s.", design->twines.str(proc_name).c_str());
}
RTLIL::Process *proc = current_module->addProcess(std::move(proc_name));
proc->attributes = std::move(attrbuf);
@@ -959,7 +995,7 @@ struct RTLILFrontendWorker {
if (try_parse_keyword("update")) {
RTLIL::SigSpec s1 = parse_sigspec();
RTLIL::SigSpec s2 = parse_sigspec();
rule->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
rule->actions.push_back({std::move(s1), std::move(s2)});
expect_eol();
continue;
}
@@ -975,7 +1011,7 @@ struct RTLILFrontendWorker {
RTLIL::MemWriteAction act;
act.attributes = std::move(attrbuf);
act.memid = parse_id();
act.memid = parse_twine();
act.address = parse_sigspec();
act.data = parse_sigspec();
act.enable = parse_sigspec();
@@ -1015,10 +1051,17 @@ struct RTLILFrontendWorker {
expect_eol();
continue;
}
if (try_parse_keyword("twines")) {
parse_twines();
continue;
}
error("Unexpected token: %s", error_token());
}
if (attrbuf.size() != 0)
error("dangling attribute");
twine_parser_holds.clear();
twine_remap.clear();
}
};