Emil J 2750a02e0c Merge pull request #6264 from YosysHQ/emil/read_verilog-array-signedness ...

read_verilog: fix sign extension in array pattern assignments

2026-10-01 13:56:38 +00:00

..

aiger

read_xaiger: skip symbol table instead of crashing since its handling was removed

2026-09-30 11:43:00 +02:00

ast

read_verilog: fix sign extension in array pattern assignments

2026-09-30 12:59:01 +02:00

blif

abc: re-isolate autoidx churn

2026-09-10 18:16:57 +02:00

json

json: read 'signed' attribute on netnames, matching ports

2026-08-20 22:20:24 -07:00

liberty

Don't mark cells w no unput as boxes.

2026-09-21 16:58:03 +02:00

rpc

Migrate build system to CMake

2026-06-03 08:58:10 +00:00

rtlil

long long to int truncation checks

2026-07-10 14:36:39 +02:00

slang

Update sv-elab and slang to v12.0

2026-09-29 18:09:25 +02:00

verific

logger: make log_verific_callback simple

2026-09-22 13:15:32 +02:00

verilog

read_verilog logging to_src() - > to_loc()

2026-09-16 12:30:40 +02:00

CMakeLists.txt

Revert "Temporarily revert #6101 and #6077"

2026-09-10 09:09:13 +02:00