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read_verilog logging to_src() - > to_loc()

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This commit is contained in:
Miodrag Milanovic
2026-09-16 12:30:40 +02:00
parent 3384d5f099
commit 7149b19f64
7 changed files with 31 additions and 31 deletions
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frontends/ast/ast.cc
+2 -2
View File
@@ -1460,7 +1460,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (design->has(child->str)) {
RTLIL::Module *existing_mod = design->module(child->str);
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error(child->location.to_src(), "Re-definition of module `%s'!\n", child->str);
log_file_error(child->location.to_loc(), "Re-definition of module `%s'!\n", child->str);
} else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s.\n",
child->str.c_str(), child->loc_string().c_str());
@@ -1938,7 +1938,7 @@ void AstModule::loadconfig() const
void AstNode::formatted_input_error(std::string_view format, std::string str) const
{
logger().formatted_error(location.to_src(), "ERROR:", format, std::move(str));
logger().formatted_error(location.to_loc(), "ERROR:", format, std::move(str));
}
YOSYS_NAMESPACE_END
frontends/ast/genrtlil.cc
+15 -15
View File
@@ -840,7 +840,7 @@ struct AST_INTERNAL::ProcessGenerator
node->detectSignWidth(width, is_signed, nullptr);
VerilogFmtArg arg = {};
arg.src = node->location.to_src();
arg.src = node->location.to_loc();
if (node->type == AST_CONSTANT && node->is_string) {
arg.type = VerilogFmtArg::STRING;
arg.str = node->bitsAsConst().decode_string();
@@ -866,7 +866,7 @@ struct AST_INTERNAL::ProcessGenerator
fmt.append_literal("\n");
fmt.emit_rtlil(cell);
} else if (!ast->str.empty()) {
log_file_error(ast->location.to_src(), "Found unsupported invocation of system task `%s'!\n", ast->str);
log_file_error(ast->location.to_loc(), "Found unsupported invocation of system task `%s'!\n", ast->str);
}
break;
@@ -918,7 +918,7 @@ struct AST_INTERNAL::ProcessGenerator
cell->set_bool_attribute(ID(keep));
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(ast->location.to_src(), "Attribute `%s' with non-constant value!\n", attr.first);
log_file_error(ast->location.to_loc(), "Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
cell->setParam(ID::FLAVOR, flavor);
@@ -1528,7 +1528,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
RTLIL::SigSpec sig = realAsConst(width_hint);
log_file_warning(location.to_src(), "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
log_file_warning(location.to_loc(), "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
return sig;
}
@@ -1553,7 +1553,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->name = str;
if (flag_autowire)
log_file_warning(location.to_src(), "Identifier `%s' is implicitly declared.\n", str);
log_file_warning(location.to_loc(), "Identifier `%s' is implicitly declared.\n", str);
else
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
}
@@ -1658,10 +1658,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset = source_width - (chunk.offset + chunk.width);
if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) {
if (chunk.width == 1)
log_file_warning(location.to_src(), "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
log_file_warning(location.to_loc(), "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
str.c_str());
else
log_file_warning(location.to_src(), "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
log_file_warning(location.to_loc(), "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
} else {
@@ -1675,10 +1675,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset += add_undef_bits_lsb;
}
if (add_undef_bits_lsb)
log_file_warning(location.to_src(), "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
log_file_warning(location.to_loc(), "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
if (add_undef_bits_msb)
log_file_warning(location.to_src(), "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
log_file_warning(location.to_loc(), "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
}
}
@@ -2081,7 +2081,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
new_left.append(left[i]);
new_right.append(right[i]);
}
log_file_warning(location.to_src(), "Ignoring assignment to constant bits:\n"
log_file_warning(location.to_loc(), "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n",
log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right));
@@ -2114,7 +2114,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
const auto* value = child->children[0].get();
if (value->type == AST_REALVALUE)
log_file_warning(location.to_src(), "Replacing floating point parameter %s.%s = %f with string.\n",
log_file_warning(location.to_loc(), "Replacing floating point parameter %s.%s = %f with string.\n",
cell, paraname.unescape(), value->realvalue);
else if (value->type != AST_CONSTANT)
input_error("Parameter %s.%s with non-constant value!\n",
@@ -2215,14 +2215,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int sz = children.size();
if (str == "$info") {
if (sz > 0)
log_file_info(location.to_src(), "%s.\n", children[0]->str);
log_file_info(location.to_loc(), "%s.\n", children[0]->str);
else
log_file_info(location.to_src(), "\n");
log_file_info(location.to_loc(), "\n");
} else if (str == "$warning") {
if (sz > 0)
log_file_warning(location.to_src(), "%s.\n", children[0]->str);
log_file_warning(location.to_loc(), "%s.\n", children[0]->str);
else
log_file_warning(location.to_src(), "\n");
log_file_warning(location.to_loc(), "\n");
} else if (str == "$error") {
if (sz > 0)
input_error("%s.\n", children[0]->str);
frontends/ast/simplify.cc
+4 -4
View File
@@ -149,7 +149,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_
while (node_arg->simplify(true, stage, -1, false)) { }
VerilogFmtArg arg = {};
arg.src = location.to_src();
arg.src = location.to_loc();
if (node_arg->type == AST_CONSTANT && node_arg->is_string) {
arg.type = VerilogFmtArg::STRING;
arg.str = node_arg->bitsAsConst().decode_string();
@@ -1177,7 +1177,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
// note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" ||
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
log_file_warning(location.to_src(), "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str);
log_file_warning(location.to_loc(), "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str);
delete_children();
str = std::string();
}
@@ -1187,7 +1187,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo"))
{
if (!current_always) {
log_file_warning(location.to_src(), "System task `%s' outside initial or always block is unsupported.\n", str);
log_file_warning(location.to_loc(), "System task `%s' outside initial or always block is unsupported.\n", str);
delete_children();
str = std::string();
} else {
@@ -2361,7 +2361,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
if (children[0]->type == AST_REALVALUE) {
RTLIL::Const constvalue = children[0]->realAsConst(width);
log_file_warning(location.to_src(), "converting real value %e to binary %s.\n",
log_file_warning(location.to_loc(), "converting real value %e to binary %s.\n",
children[0]->realvalue, log_signal(constvalue));
children[0] = mkconst_bits(location, constvalue.to_bits(), sign_hint);
fixup_hierarchy_flags();
frontends/verilog/const2ast.cc
+2 -2
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@@ -47,7 +47,7 @@ using namespace VERILOG_FRONTEND;
void ConstParser::log_maybe_loc_error(std::string msg) {
if (loc.begin.filename)
log_file_error(loc.to_src(), "%s", msg);
log_file_error(loc.to_loc(), "%s", msg);
else if (!Frontend::current_script_filename.empty())
log_file_error(LogSourceLocation(Frontend::current_script_filename, Frontend::current_script_lineno),
"Failed to parse constant `%s': %s", code_str, msg);
@@ -57,7 +57,7 @@ void ConstParser::log_maybe_loc_error(std::string msg) {
void ConstParser::log_maybe_loc_warn(std::string msg) {
if (loc.begin.filename)
log_file_warning(loc.to_src(), "%s", msg);
log_file_warning(loc.to_loc(), "%s", msg);
else if (!Frontend::current_script_filename.empty())
log_file_warning(LogSourceLocation(Frontend::current_script_filename, Frontend::current_script_lineno),
"While parsing constant `%s': %s", code_str, msg);
frontends/verilog/verilog_error.cc
+2 -2
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@@ -34,10 +34,10 @@ USING_YOSYS_NAMESPACE
[[noreturn]]
void VERILOG_FRONTEND::formatted_err_at_loc(Location loc, std::string str)
{
YOSYS_NAMESPACE_PREFIX log_file_error(loc.to_src(), "%s\n", std::move(str));
YOSYS_NAMESPACE_PREFIX log_file_error(loc.to_loc(), "%s\n", std::move(str));
}
void VERILOG_FRONTEND::formatted_warn_at_loc(Location loc, std::string str)
{
YOSYS_NAMESPACE_PREFIX log_file_warning(loc.to_src(), "%s\n", std::move(str));
YOSYS_NAMESPACE_PREFIX log_file_warning(loc.to_loc(), "%s\n", std::move(str));
}
frontends/verilog/verilog_lexer.l
+5 -5
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@@ -162,7 +162,7 @@ static bool is_hex_dig(char c, int *val, parser::location_type loc)
*val = c - 'A' + 0xA;
return true;
} else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') {
log_file_warning(loc.to_src(), "'%c' not a valid digit in hex escape sequence.\n", c);
log_file_warning(loc.to_loc(), "'%c' not a valid digit in hex escape sequence.\n", c);
*val = 0; // not semantically valid in hex escape...
return true; // ...but still processed as part of hex token
}
@@ -176,7 +176,7 @@ static bool is_oct_dig(char c, int *val, parser::location_type loc)
*val = c - '0';
return true;
} else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') {
log_file_warning(loc.to_src(), "'%c' not a valid digit in octal escape sequence.\n", c);
log_file_warning(loc.to_loc(), "'%c' not a valid digit in octal escape sequence.\n", c);
*val = 0; // not semantically valid in octal escape...
return true; // ...but still processed as part of octal token
}
@@ -196,7 +196,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser::
if (in + 1 < str + len && (in[1] ^ *in) == ('\n' ^ '\r'))
in++;
if (!triple)
log_file_warning(loc.to_src(), "Multi-line string literals should be triple-quoted or escaped.\n");
log_file_warning(loc.to_loc(), "Multi-line string literals should be triple-quoted or escaped.\n");
*out++ = '\n';
break;
case '\\':
@@ -233,7 +233,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser::
}
out++;
} else
log_file_warning(loc.to_src(), "ignoring invalid hex escape.\n");
log_file_warning(loc.to_loc(), "ignoring invalid hex escape.\n");
break;
case '\\':
*out++ = '\\';
@@ -256,7 +256,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser::
in++;
if (in + 1 < str + len && is_oct_dig(in[1], &val, loc)) {
if (*out >= 040)
log_file_warning(loc.to_src(), "octal escape exceeds \\377\n");
log_file_warning(loc.to_loc(), "octal escape exceeds \\377\n");
*out = *out * 010 + val;
in++;
}
frontends/verilog/verilog_location.h
+1 -1
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@@ -89,7 +89,7 @@ struct Location {
return oss.str();
}
YOSYS_NAMESPACE_PREFIX LogSourceLocation to_src() const {
YOSYS_NAMESPACE_PREFIX LogSourceLocation to_loc() const {
return YOSYS_NAMESPACE_PREFIX LogSourceLocation(begin.filename ? *(begin.filename) : "UNKNOWN", begin.line, begin.column, end.line, end.column);
}
};