Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8

abc_ops_reintegrate: xaiger2 compatibility

backends/aiger2/aiger.cc

@@ -998,7 +998,7 @@ struct XAigerWriter : AigerWriter {
 			if (map_file.is_open() && !box_port) {
 				log_assert(cursor.is_top()); // TODO
 				driven_by_opaque_box.insert(bit);
-				map_file << "pi " << pis.size() - 1 << " " << bit.offset
+				map_file << "input " << pis.size() - 1 << " " << bit.offset
 						<< " " << bit.wire->name.c_str() << "\n";
 			}
 		} else {
@@ -1273,11 +1273,8 @@ struct XAigerWriter : AigerWriter {
 		for (auto w : top->wires())
 			if (w->port_output)
 				for (int i = 0; i < w->width; i++) {
-					// When a module output is directly driven by an opaque box, we
-					// don't emit it to the mapping file to aid re-integration, but we
-					// do emit a proper PO.
-					if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) {
-						map_file << "po " << proper_pos_counter << " " << i
+					if (map_file.is_open()) {
+						map_file << "output " << proper_pos_counter << " " << i
 									<< " " << w->name.c_str() << "\n";
 					}
 					proper_pos_counter++;

frontends/aiger/aigerparse.cc

@@ -480,19 +480,22 @@ void AigerReader::parse_xaiger()
 				mapping_cell.type = RTLIL::escape_id(cellName);
 				mapping_cell.out = RTLIL::escape_id(outPinName);
 
-				auto module = design->addModule(RTLIL::escape_id(cellName));
-				module->set_bool_attribute(ID::blackbox);
-				module->addWire(RTLIL::escape_id(outPinName))->port_output = true;
-
 				for (unsigned j = 0; j < inPinNum; ++j) {
 					auto inPinName = std::string{};
 					std::getline(f, inPinName, '\0');
 					log_debug2("M:    inPinName=%s\n", inPinName);
 					mapping_cell.ins.push_back(RTLIL::escape_id(inPinName));
-					module->addWire(RTLIL::escape_id(inPinName))->port_input = true;
 				}
 
-				module->fixup_ports();
+				if (!design->module(mapping_cell.type)) {
+					auto module = design->addModule(mapping_cell.type);
+					module->set_bool_attribute(ID::blackbox);
+					module->addWire(mapping_cell.out)->port_output = true;
+					for (unsigned j = 0; j < inPinNum; ++j) {
+						module->addWire(mapping_cell.ins.at(j))->port_input = true;
+					}
+					module->fixup_ports();
+				}
 
 				mapping_cells.push_back(std::move(mapping_cell));
 			}
@@ -522,6 +525,7 @@ void AigerReader::parse_xaiger()
 				}
 
 				RTLIL::Cell *cell = module->addCell(stringf("$sc$aiger%d$%d", aiger_autoidx, rootNodeID), mapping_cell.type);
+				cell->set_bool_attribute(ID::abc9_cell);
 				cell->setPort(mapping_cell.out, output_sig);
 
 				for (unsigned j = 0; j < mapping_cell.ins.size(); ++j) {

frontends/aiger2/xaiger.cc

@@ -123,7 +123,7 @@ struct Xaiger2Frontend : public Frontend {
 
 		std::string type;
 		while (map_file >> type) {
-			if (type == "pi") {
+			if (type == "input") {
 				int pi_idx;
 				int woffset;
 				std::string name;
@@ -398,7 +398,7 @@ struct Xaiger2Frontend : public Frontend {
 		map_file.close();
 		map_file.open(map_filename);
 		while (map_file >> type) {
-			if (type == "po") {
+			if (type == "output") {
 				int po_idx;
 				int woffset;
 				std::string name;

kernel/constids.inc

@@ -827,6 +827,7 @@ X(abc9_box_id)
 X(abc9_box_seq)
 X(abc9_bypass)
 X(abc9_carry)
+X(abc9_cell)
 X(abc9_deferred_box)
 X(abc9_flop)
 X(abc9_keep)

passes/techmap/abc_new.cc

@@ -193,8 +193,9 @@ struct AbcNewPass : public ScriptPass {
 				run(stringf("  abc9_ops -write_box %s/input.box", tmpdir));
 				run(stringf("  write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
 				run(stringf("  abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
-				run(stringf("  read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
-							modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
+				run(stringf("  read_aiger -xaiger -module_name %s$abc9 %s/output.aig",
+							modname, tmpdir));
+				run(stringf("  abc_ops_reintegrate -map %s/input.map2", tmpdir));
 				if (!help_mode && mod->has_attribute(ID(abc9_script))) {
 					if (script_save.empty())
 						active_design->scratchpad_unset("abc9.script");

passes/techmap/abc_ops_reintegrate.cc

@@ -50,6 +50,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 	int co_count = design->scratchpad_get_int("read_aiger.co_count", 0);
 
 	dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
+	dict<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> pseudopos;
 
 	if (!map_filename.empty()) {
 		std::ifstream mf(map_filename);
@@ -150,6 +151,28 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 					}
 				}
 			}
+			else if (type == "pseudopo") {
+				std::string port;
+				mf >> port;
+				RTLIL::IdString escaped_p = RTLIL::escape_id(port);
+
+				log_assert(variable + co_count < output_count);
+				RTLIL::IdString wire_name = stringf("$aiger$o%d", variable + co_count);
+				RTLIL::Wire* wire = mapped_mod->wire(wire_name);
+				log_assert(wire);
+				log_assert(wire->port_output);
+				log_debug("Mapping pseudo output %s", wire);
+
+				if (index == 0) {
+					pseudopos.insert({wire_name, std::make_pair(escaped_s, escaped_p)});
+					log_debug(" -> %s.%s\n", escaped_s, escaped_p);
+				}
+				else {
+					RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
+					pseudopos.insert({wire_name, std::make_pair(indexed_name, escaped_p)});
+					log_debug(" -> %s.%s\n", indexed_name, escaped_p);
+				}
+			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = mapped_mod->cell(stringf("$box%d", variable));
 				if (!cell)
@@ -352,7 +375,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 			continue;
 		}
 
-		if (mapped_cell->type == ID($lut)) {
+		if (mapped_cell->type == ID($lut) || mapped_cell->get_bool_attribute(ID::abc9_cell)) {
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
 			cell->attributes = mapped_cell->attributes;
@@ -506,6 +529,24 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 		log("ABC RESULTS:   %15s cells: %8d\n", it.first, it.second);
 	int in_wires = 0, out_wires = 0;
 
+	for (auto pseudopo : pseudopos) {
+		auto wire_name = pseudopo.first;
+		auto box_name = pseudopo.second.first;
+		auto box_port_name = pseudopo.second.second;
+
+		RTLIL::Wire *mapped_wire = mapped_mod->wire(wire_name);
+		log_assert(mapped_wire);
+		auto box = module->cell(box_name);
+		log_assert(box);
+
+		RTLIL::Wire *remap_wire = module->wire(remap_name(wire_name));
+		box->setPort(box_port_name, remap_wire);
+
+		mapped_wire->port_output = false;
+	}
+
+	mapped_mod->fixup_ports();
+
 	// Stitch in mapped_mod's inputs/outputs into module
 	for (auto port : mapped_mod->ports) {
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);

tests/arch/gatemate/logic.ys

@@ -27,7 +27,7 @@ design -load orig
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_LUT1
-select -assert-count 6 t:CC_LUT2
+select -assert-count 4 t:CC_LUT1
+select -assert-count 3 t:CC_LUT2
 select -assert-count 2 t:CC_L2T4
 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D

tests/arch/gatemate/luttrees.ys

@@ -30,5 +30,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd luttrees # Constrain all select calls below inside the top module
 
-select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
-select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
+select -assert-count 917 t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
+select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D

tests/techmap/abc_new.ys

@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module sub(input a, b, c, output y);
+  assign y = (a & b) | c;
+endmodule
+module top(input a, b, c, d, output y, z);
+  assign z = (a ^ b) & d;
+  sub s_i (.a(a), .b(b), .c(c), .y(y));
+endmodule
+EOT
+hierarchy -top top
+techmap
+abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib
+

tests/techmap/xaiger2-5169.ys

@@ -56,5 +56,5 @@ endmodule
 
 EOF
 
-logger -expect error "Malformed design" 1
+logger -expect error "Cannot find existing box cell" 1
 abc_new -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib