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verific: twines

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:01 +02:00
parent bd2009bcca
commit 080e46417a
4 changed files with 35 additions and 31 deletions
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frontends/verific/verific.cc
+31 -29
View File
@@ -267,7 +267,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
if (obj->Linefile())
s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())), Verific::LineFile::GetLineNo(obj->Linefile()));
s += stringf("$%d", autoidx++);
return s;
return module->twines().add(std::move(s));
}
static const RTLIL::Const extract_vhdl_boolean(std::string &val)
@@ -455,7 +455,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
FOREACH_ATTRIBUTE(obj, mi, attr) {
if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
continue;
attributes[RTLIL::escape_id(attr->Key())] = verific_const(nullptr, attr->Value(), obj);
attributes[module->twines().add(RTLIL::escape_id(attr->Key()))] = verific_const(nullptr, attr->Value(), obj);
}
if (nl) {
@@ -500,7 +500,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
if (nl->IsFromVerilog()) {
auto const value = verific_const(type_name, v, nl, false);
attributes.emplace(stringf("\\enum_value_%s", value.as_string()), RTLIL::escape_id(k));
attributes.emplace(module->twines().add(stringf("\\enum_value_%s", value.as_string())), RTLIL::escape_id(k));
}
#ifdef VERIFIC_VHDL_SUPPORT
else if (nl->IsFromVhdl()) {
@@ -513,7 +513,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
strncpy(q, p, l);
q[l] = '\0';
for(char *ptr = q; *ptr; ++ptr )*ptr = tolower(*ptr);
attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
attributes.emplace(module->twines().add(stringf("\\enum_value_%s", q)), RTLIL::escape_id(k));
} else {
auto *q = p+1;
for (; *q != '"'; q++)
@@ -530,7 +530,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
auto q = (char*)malloc(l+1-2);
strncpy(q, p+1, l-2);
q[l-2] = '\0';
attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
attributes.emplace(module->twines().add(stringf("\\enum_value_%s", q)), RTLIL::escape_id(k));
free(q);
}
}
@@ -1553,14 +1553,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
netlist = nl;
if (design->has(module_name)) {
IdString module_id = design->twines.add(module_name);
if (design->has(module_id)) {
if (!nl->IsOperator() && !is_blackbox(nl))
log_cmd_error("Re-definition of module `%s'.\n", netlist_name);
return;
}
module = new RTLIL::Module;
module->name = module_name;
module->design = design;
module->name = module_id;
design->add(module);
if (is_blackbox(nl)) {
@@ -1584,10 +1586,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
const char *param_value ;
MapIter mi;
FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
module->avail_parameters(RTLIL::escape_id(param_name));
IdString param_id = design->twines.add(RTLIL::escape_id(param_name));
module->avail_parameters(param_id);
const TypeRange *tr = nl->GetTypeRange(param_name) ;
const char* type_name = (tr) ? tr->GetTypeName() : nullptr;
module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(type_name, param_value, nl);
module->parameter_default_values[param_id] = verific_const(type_name, param_value, nl);
}
SetIter si;
@@ -1695,10 +1698,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
{
if (net->IsRamNet())
{
RTLIL::Memory *memory = new RTLIL::Memory;
memory->name = RTLIL::escape_id(net->Name());
log_assert(module->count_id(memory->name) == 0);
module->memories[memory->name] = memory;
IdString memory_name = design->twines.add(RTLIL::escape_id(net->Name()));
log_assert(module->count_id(memory_name) == 0);
RTLIL::Memory *memory = module->addMemory(memory_name);
import_attributes(memory->attributes, net, nl);
int number_of_bits = net->Size();
@@ -1809,12 +1811,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (net->Bus())
continue;
RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : new_verific_id(net));
if (verific_verbose)
log(" importing net %s as %s.\n", net->Name(), wire_name.unescape());
RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? design->twines.add(RTLIL::escape_id(net->Name())) : new_verific_id(net));
RTLIL::Wire *wire = module->addWire(wire_name);
if (verific_verbose)
log(" importing net %s as %s.\n", net->Name(), wire->name.unescape());
import_attributes(wire->attributes, net, nl, 1);
net_map[net] = wire;
@@ -1833,12 +1835,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (found_new_net)
{
RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(netbus->Name()) : new_verific_id(netbus));
if (verific_verbose)
log(" importing netbus %s as %s.\n", netbus->Name(), wire_name.unescape());
RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? design->twines.add(RTLIL::escape_id(netbus->Name())) : new_verific_id(netbus));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
if (verific_verbose)
log(" importing netbus %s as %s.\n", netbus->Name(), wire->name.unescape());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
wire->upto = netbus->IsUp();
MapIter mibus;
@@ -1966,10 +1968,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
{
RTLIL::IdString inst_name = module->uniquify(mode_names || inst->IsUserDeclared() ? RTLIL::escape_id(inst->Name()) : new_verific_id(inst));
RTLIL::IdString inst_name = module->uniquify(mode_names || inst->IsUserDeclared() ? design->twines.add(RTLIL::escape_id(inst->Name())) : new_verific_id(inst));
if (verific_verbose)
log(" importing cell %s (%s) as %s.\n", inst->Name(), inst->View()->Owner()->Name(), inst_name.unescape());
log(" importing cell %s (%s) as %s.\n", inst->Name(), inst->View()->Owner()->Name(), PooledName(design, inst_name).unescape());
if (mode_verific)
goto import_verific_cells;
@@ -2003,7 +2005,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (inst->Type() == OPER_READ_PORT)
{
RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr);
RTLIL::Memory *memory = module->memories.at(module->twines().find(RTLIL::escape_id(inst->GetInput()->Name())), nullptr);
if (!memory)
log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
@@ -2016,7 +2018,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memrd));
module->twines().add(inst_name, stringf("_%d", i)), ID($memrd));
cell->parameters[ID::MEMID] = memory->name.str();
cell->parameters[ID::CLK_ENABLE] = false;
cell->parameters[ID::CLK_POLARITY] = true;
@@ -2034,7 +2036,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
{
RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
RTLIL::Memory *memory = module->memories.at(module->twines().find(RTLIL::escape_id(inst->GetOutput()->Name())), nullptr);
if (!memory)
log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
int numchunks = int(inst->Input2Size()) / memory->width;
@@ -2046,7 +2048,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memwr));
module->twines().add(inst_name, stringf("_%d", i)), ID($memwr));
cell->parameters[ID::MEMID] = memory->name.str();
cell->parameters[ID::CLK_ENABLE] = false;
cell->parameters[ID::CLK_POLARITY] = true;
@@ -2318,7 +2320,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
port_offset = abs(port_offset - (lsb_index - min(msb_index, lsb_index)));
}
}
IdString port_name_id = RTLIL::escape_id(port_name);
IdString port_name_id = module->twines().add(RTLIL::escape_id(port_name));
auto &sigvec = cell_port_conns[port_name_id];
if (GetSize(sigvec) <= port_offset) {
SigSpec zwires = module->addWire(new_verific_id(inst), port_offset+1-GetSize(sigvec));
@@ -2333,7 +2335,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
for (auto &it : cell_port_conns) {
if (verific_verbose)
log(" .%s(%s)\n", it.first.unescape(), log_signal(it.second));
log(" .%s(%s)\n", PooledName(module, it.first).unescape(), log_signal(it.second));
cell->setPort(it.first, it.second);
}
}
frontends/verific/verific.h
+2
View File
@@ -52,6 +52,8 @@ struct VerificClocking {
RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);
RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);
RTLIL::Cell *addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q);
YS_NAME_FWD_POOL(addDff, module->twines()) YS_NAME_FWD_POOL(addAdff, module->twines())
YS_NAME_FWD_POOL(addDffsr, module->twines()) YS_NAME_FWD_POOL(addAldff, module->twines())
bool property_matches_sequence(const VerificClocking &seq) const {
if (clock_net != seq.clock_net)
frontends/verific/verificsva.cc
+1 -1
View File
@@ -1745,7 +1745,7 @@ struct VerificSvaImporter
}
}
RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID);
RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? module->twines().add(RTLIL::escape_id(root->Name())) : module->twines().add(NEW_ID));
try
{
passes/hierarchy/hierarchy.cc
+1 -1
View File
@@ -1069,7 +1069,7 @@ struct HierarchyPass : public Pass {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
top_mod = design->module(design->twines.find(RTLIL::escape_id(load_top_mod)));
}
#endif
if (top_mod == NULL)