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twines: reduce structural loss

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:02 +02:00
parent 9e00bd6421
commit d5decad312
3 changed files with 30 additions and 26 deletions
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frontends/ast/genrtlil.cc
+21 -17
View File
@@ -163,7 +163,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
return wire;
}
static void check_unique_id(RTLIL::Module *module, const std::string &id,
static void check_unique_id(RTLIL::Module *module, IdString id,
const AstNode *node, const char *to_add_kind)
{
auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) {
@@ -172,18 +172,23 @@ static void check_unique_id(RTLIL::Module *module, const std::string &id,
if (!src.empty())
location_str = "at " + src;
node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n",
to_add_kind, id.c_str(), existing_kind, location_str.c_str());
to_add_kind, module->twines().str(id), existing_kind, location_str.c_str());
};
IdString id_tw = intern_hier_name(module->design, id);
if (const RTLIL::Wire *wire = module->wire(id_tw))
if (const RTLIL::Wire *wire = module->wire(id))
already_exists(wire, "signal");
if (const RTLIL::Cell *cell = module->cell(id_tw))
if (const RTLIL::Cell *cell = module->cell(id))
already_exists(cell, "cell");
if (module->processes.count(id_tw))
already_exists(module->processes.at(id_tw), "process");
if (module->memories.count(id_tw))
already_exists(module->memories.at(id_tw), "memory");
if (module->processes.count(id))
already_exists(module->processes.at(id), "process");
if (module->memories.count(id))
already_exists(module->memories.at(id), "memory");
}
static void check_unique_id(RTLIL::Module *module, const std::string &id,
const AstNode *node, const char *to_add_kind)
{
check_unique_id(module, intern_hier_name(module->design, id), node, to_add_kind);
}
// helper class for rewriting simple lookahead references in AST always blocks
@@ -892,7 +897,7 @@ struct AST_INTERNAL::ProcessGenerator
stringf("$%s", flavor), autoidx++);
else
cellname = current_module->twines().add(std::string{ast->str});
check_unique_id(current_module, current_module->twines().str(cellname), ast, "procedural assertion");
check_unique_id(current_module, cellname, ast, "procedural assertion");
RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
if (GetSize(check) != 1)
@@ -957,25 +962,24 @@ struct AST_INTERNAL::ProcessGenerator
for (auto& child : always->children)
if (child->type == AST_MEMWR)
{
std::string memid = child->str;
std::string memid_str = child->str;
int portid = child->children[3]->asInt(false);
int cur_idx = GetSize(sync->mem_write_actions);
RTLIL::MemWriteAction action;
set_src_attr(&action, child.get());
action.memid = current_module->twines().add(std::string(memid));
action.memid = current_module->twines().add(memid_str);
action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
IdString memid_tw = current_module->twines().find(memid);
action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid_tw]->width, true, &subst_rvalue_map.stdmap());
action.data = child->children[1]->genWidthRTLIL(current_module->memories[action.memid]->width, true, &subst_rvalue_map.stdmap());
action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst();
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
for (int i = 0; i < portid; i++) {
int new_bit = port_map[std::make_pair(memid, i)];
int new_bit = port_map[std::make_pair(memid_str, i)];
priority_mask.set(new_bit, orig_priority_mask[i]);
}
action.priority_mask = priority_mask;
sync->mem_write_actions.push_back(action);
port_map[std::make_pair(memid, portid)] = cur_idx;
port_map[std::make_pair(memid_str, portid)] = cur_idx;
}
}
};
@@ -2050,7 +2054,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
stringf("$%s", flavor), autoidx++);
else
cellname = current_module->twines().add(std::string{str});
check_unique_id(current_module, current_module->twines().str(cellname), this, "procedural assertion");
check_unique_id(current_module, cellname, this, "procedural assertion");
RTLIL::SigSpec check = children[0]->genRTLIL();
if (GetSize(check) != 1)
passes/hierarchy/submod.cc
+5 -4
View File
@@ -152,9 +152,9 @@ struct SubmodWorker
if (!flags.is_int_driven.is_fully_zero() && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
std::string new_wire_name = wire->name.str();
std::string new_wire_name;
if (new_wire_port_input || new_wire_port_output) {
if (new_wire_name[0] == '$')
if (!wire->name.isPublic())
while (1) {
std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++);
if (all_wire_names.count(next_wire_name) == 0) {
@@ -164,10 +164,11 @@ struct SubmodWorker
}
}
else if (hidden_mode)
new_wire_name = stringf("$submod%s", new_wire_name);
new_wire_name = stringf("$submod%s", wire->name.str());
}
RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
IdString new_wire_ref = new_wire_name.empty() ? IdString(wire->name) : IdString(design->twines.add(new_wire_name));
RTLIL::Wire *new_wire = new_mod->addWire(new_wire_ref, wire->width);
new_wire->port_input = new_wire_port_input;
new_wire->port_output = new_wire_port_output;
new_wire->start_offset = wire->start_offset;
passes/techmap/techmap.cc
+4 -5
View File
@@ -202,10 +202,9 @@ struct TechmapWorker
log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
}
std::string orig_cell_name;
IdString orig_cell_ref = cell->name;
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
orig_cell_name = cell->name.str();
for (auto tpl_cell : tpl->cells())
if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) {
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
@@ -274,7 +273,7 @@ struct TechmapWorker
std::string tpl_w_name = tpl_w->name.str();
if (const char *p = strstr(tpl_w_name.c_str(), "_TECHMAP_REPLACE_.")) {
Wire *replace_w = module->addWire(std::string(orig_cell_name) + (p + strlen("_TECHMAP_REPLACE_")), tpl_w);
Wire *replace_w = module->addWire(module->twines().add(orig_cell_ref, p + strlen("_TECHMAP_REPLACE_")), tpl_w);
module->connect(replace_w, w);
}
}
@@ -379,9 +378,9 @@ struct TechmapWorker
std::string tpl_cell_name = tpl_cell->name.str();
IdString c_ref;
if (techmap_replace_cell)
c_ref = module->twines().add(std::string{orig_cell_name});
c_ref = orig_cell_ref;
else if (const char *p = strstr(tpl_cell_name.c_str(), "_TECHMAP_REPLACE_."))
c_ref = module->twines().add(stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_")));
c_ref = module->twines().add(orig_cell_ref, p + strlen("_TECHMAP_REPLACE_"));
else
c_ref = ap.name(tpl_cell->name);