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rtlil: remove dead verilog bindings

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This commit is contained in:
Emil J. Tywoniak
2026-08-31 22:13:01 +02:00
parent c30457480f
commit fbd7c249ec
28 changed files with 5 additions and 494 deletions
Download Patch File Download Diff File Expand all files Collapse all files
frontends/ast/CMakeLists.txt
-2
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@@ -1,6 +1,4 @@
yosys_core(ast
ast_binding.cc
ast_binding.h
ast.cc
ast.h
dpicall.cc
frontends/ast/ast.cc
-6
View File
@@ -179,7 +179,6 @@ std::string AST::type2str(AstNodeType type)
X(AST_STRUCT)
X(AST_UNION)
X(AST_STRUCT_ITEM)
X(AST_BIND)
#undef X
default:
log_abort();
@@ -1478,11 +1477,6 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
design->verilog_packages.push_back(child->clone());
current_scope.clear();
}
else if (child->type == AST_BIND) {
// top-level bind construct
for (RTLIL::Binding *binding : child->genBindings())
design->add(binding);
}
else {
// must be global definition
if (child->type == AST_PARAMETER)
frontends/ast/ast.h
+1 -5
View File
@@ -161,8 +161,7 @@ namespace AST
AST_TYPEDEF,
AST_STRUCT,
AST_UNION,
AST_STRUCT_ITEM,
AST_BIND
AST_STRUCT_ITEM
};
using AstSrcLocType = Location;
@@ -298,9 +297,6 @@ namespace AST
void dumpAst(FILE *f, std::string indent) const;
void dumpVlog(FILE *f, std::string indent) const;
// Generate RTLIL for a bind construct
std::vector<RTLIL::Binding *> genBindings() const;
// used by genRTLIL() for detecting expression width and sign
void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = nullptr);
void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = nullptr);
frontends/ast/ast_binding.cc
-49
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@@ -1,49 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "ast_binding.h"
#include "ast.h"
YOSYS_NAMESPACE_BEGIN
using namespace AST_INTERNAL;
AST::Binding::Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name,
const AstNode &cell)
: RTLIL::Binding(target_type, target_name),
ast_node(cell.clone())
{
log_assert(cell.type == AST_CELL);
}
std::string
AST::Binding::describe() const
{
std::ostringstream oss;
oss << "directive to bind " << ast_node->str
<< " to " << target_name.str();
if (!target_type.empty())
oss << " (target type: "
<< target_type.str()
<< ")";
return oss.str();
}
PRIVATE_NAMESPACE_END
frontends/ast/ast_binding.h
-58
View File
@@ -1,58 +0,0 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* This header declares the AST::Binding class
*
* This is used to support the bind directive and is to RTLIL::Binding as
* AST::AstModule is to RTLIL::Module, holding a syntax-level representation of
* cells until we get to a stage where they make sense. In the case of a bind
* directive, this is when we elaborate the design in the hierarchy pass.
*
*/
#ifndef AST_BINDING_H
#define AST_BINDING_H
#include "kernel/rtlil.h"
#include "kernel/binding.h"
#include <memory>
YOSYS_NAMESPACE_BEGIN
namespace AST
{
class Binding : public RTLIL::Binding
{
public:
Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name,
const AstNode &cell);
std::string describe() const override;
private:
// The syntax-level representation of the cell to be bound.
std::unique_ptr<AstNode> ast_node;
};
}
YOSYS_NAMESPACE_END
#endif
frontends/ast/genrtlil.cc
+1 -80
View File
@@ -28,10 +28,8 @@
#include "kernel/log.h"
#include "kernel/utils.h"
#include "kernel/binding.h"
#include "libs/sha1/sha1.h"
#include "ast.h"
#include "ast_binding.h"
#include <sstream>
#include <stdarg.h>
@@ -979,69 +977,6 @@ struct AST_INTERNAL::ProcessGenerator
}
};
// Generate RTLIL for a bind construct
//
// The AST node will have one or more AST_IDENTIFIER children, which were added
// by bind_target_instance in the parser. After these, it will have one or more
// cells, as parsed by single_cell. These have type AST_CELL.
//
// If there is more than one AST_IDENTIFIER, the first one should be considered
// a module identifier. If there is only one AST_IDENTIFIER, we can't tell at
// this point whether it's a module/interface name or the name of an instance
// because the correct interpretation depends on what's visible at elaboration
// time. For now, we just treat it as a target instance with unknown type, and
// we'll deal with the corner case in the hierarchy pass.
//
// To simplify downstream code, RTLIL::Binding only has a single target and
// single bound instance. If we see the syntax that allows more than one of
// either, we split it into multiple Binding objects.
std::vector<RTLIL::Binding *> AstNode::genBindings() const
{
// Partition children into identifiers and cells
int num_ids = 0;
for (int i = 0; i < GetSize(children); ++i) {
if (children[i]->type != AST_IDENTIFIER) {
log_assert(i > 0);
num_ids = i;
break;
}
}
// We should have found at least one child that's not an identifier
log_assert(num_ids > 0);
// Make sense of the identifiers, extracting a possible type name and a
// list of hierarchical IDs. We represent an unknown type with an empty
// string.
RTLIL::IdString tgt_type;
int first_tgt_inst = 0;
if (num_ids > 1) {
tgt_type = children[0]->str;
first_tgt_inst = 1;
}
std::vector<RTLIL::Binding *> ret;
// At this point, we know that children with index >= first_tgt_inst and
// index < num_ids are (hierarchical?) names of target instances. Make a
// binding object for each of them, and fill in the generated instance
// cells each time.
for (int i = first_tgt_inst; i < num_ids; ++i) {
const AstNode &tgt_child = *children[i];
for (int j = num_ids; j < GetSize(children); ++j) {
const AstNode &cell_child = *children[j];
log_assert(cell_child.type == AST_CELL);
ret.push_back(new AST::Binding(tgt_type, tgt_child.str,
cell_child));
}
}
return ret;
}
// detect sign and width of an expression
void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
{
@@ -1615,14 +1550,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
set_src_attr(wire, this);
wire->name = str;
// If we are currently processing a bind directive which wires up
// signals or parameters explicitly, rather than with .*, then
// current_module will start out empty and we don't want to warn the
// user about it: we'll spot broken wiring later, when we run the
// hierarchy pass.
if (dynamic_cast<RTLIL::Binding*>(current_module)) {
/* nothing to do here */
} else if (flag_autowire)
if (flag_autowire)
log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str);
else
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
@@ -2312,13 +2240,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
} break;
case AST_BIND: {
// Read a bind construct. This should have one or more cells as children.
for (RTLIL::Binding *binding : genBindings())
current_module->add(binding);
break;
}
case AST_FCALL: {
if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
{
frontends/verilog/verilog_lexer.l
-1
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@@ -421,7 +421,6 @@ TIME_SCALE_SUFFIX [munpf]?s
"const" { if (mode->formal) return parser::make_TOK_CONST(out_loc); SV_KEYWORD(parser::make_TOK_CONST(out_loc)); }
"checker" { if (mode->formal) return parser::make_TOK_CHECKER(out_loc); SV_KEYWORD(parser::make_TOK_CHECKER(out_loc)); }
"endchecker" { if (mode->formal) return parser::make_TOK_ENDCHECKER(out_loc); SV_KEYWORD(parser::make_TOK_ENDCHECKER(out_loc)); }
"bind" { if (mode->formal) return parser::make_TOK_BIND(out_loc); SV_KEYWORD(parser::make_TOK_BIND(out_loc)); }
"final" { SV_KEYWORD(parser::make_TOK_FINAL(out_loc)); }
"logic" { SV_KEYWORD(parser::make_TOK_LOGIC(out_loc)); }
"var" { SV_KEYWORD(parser::make_TOK_VAR(out_loc)); }
frontends/verilog/verilog_parser.y
+3 -26
View File
@@ -510,7 +510,7 @@
%token TOK_BIT_OR_ASSIGN TOK_BIT_AND_ASSIGN TOK_BIT_XOR_ASSIGN TOK_ADD_ASSIGN
%token TOK_SUB_ASSIGN TOK_DIV_ASSIGN TOK_MOD_ASSIGN TOK_MUL_ASSIGN
%token TOK_SHL_ASSIGN TOK_SHR_ASSIGN TOK_SSHL_ASSIGN TOK_SSHR_ASSIGN
%token TOK_BIND TOK_TIME_SCALE
%token TOK_TIME_SCALE
%token TOK_IMPORT
%token TOK_EXCL "'!'"
@@ -610,7 +610,6 @@ design:
package design |
import_stmt design |
interface design |
bind_directive design |
%empty;
attr:
@@ -881,29 +880,7 @@ interface_body:
interface_body_stmt:
param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
modport_stmt | bind_directive;
bind_directive:
TOK_BIND {
(void)extra->pushChild(std::make_unique<AstNode>(@$, AST_BIND));
}
bind_target {
// bind_target should have added at least one child
log_assert(extra->ast_stack.back()->children.size() >= 1);
}
TOK_ID {
// The single_cell parser in cell_list_no_array uses extra->astbuf1 as
// a sort of template for constructing cells.
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_CELL);
extra->astbuf1->children.push_back(std::make_unique<AstNode>(@$, AST_CELLTYPE));
extra->astbuf1->children[0]->str = *$5;
}
cell_parameter_list_opt cell_list_no_array TOK_SEMICOL {
// cell_list should have added at least one more child
log_assert(extra->ast_stack.back()->children.size() >= 2);
(void)extra->astbuf1.reset();
extra->ast_stack.pop_back();
};
modport_stmt;
// bind_target matches the target of the bind (everything before
// bind_instantiation in the IEEE 1800 spec).
@@ -1125,7 +1102,7 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
enum_decl | struct_decl | bind_directive |
enum_decl | struct_decl |
always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
checker_decl:
kernel/CMakeLists.txt
-3
View File
@@ -15,8 +15,6 @@ foreach (library simlib simcells)
endforeach()
yosys_core(kernel
binding.cc
binding.h
bitpattern.h
calc.cc
cellaigs.cc
@@ -115,7 +113,6 @@ yosys_core(kernel
DATA_DIR
include/kernel
DATA_FILES
binding.h
bitpattern.h
cellaigs.h
celledges.h
kernel/binding.cc
-29
View File
@@ -1,29 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "binding.h"
YOSYS_NAMESPACE_BEGIN
RTLIL::Binding::Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name)
: target_type(target_type), target_name(target_name)
{}
YOSYS_NAMESPACE_END
kernel/binding.h
-60
View File
@@ -1,60 +0,0 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef BINDING_H
#define BINDING_H
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
struct RTLIL::Binding
{
// Represents a bind construct.
//
// The target of the binding is represented by target_type and
// target_name (see comments above the fields).
Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name);
virtual ~Binding() {}
// Return a string describing the binding
virtual std::string describe() const = 0;
protected:
// May be empty. If not, it's the name of the module or interface to
// bind to.
RTLIL::IdString target_type;
// If target_type is nonempty (the usual case), this is a hierarchical
// reference to the bind target. If target_type is empty, we have to
// wait until the hierarchy pass to figure out whether this was the name
// of a module/interface type or an instance.
RTLIL::IdString target_name;
// An attribute name which contains an ID that's unique across binding
// instances (used to ensure we don't apply a binding twice to a module)
RTLIL::IdString attr_name;
};
YOSYS_NAMESPACE_END
#endif
kernel/rtlil.cc
-17
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@@ -20,7 +20,6 @@
#include "kernel/yosys.h"
#include "kernel/macc.h"
#include "kernel/newcelltypes.h"
#include "kernel/binding.h"
#include "kernel/sigtools.h"
#include "kernel/threading.h"
#include "frontends/verilog/verilog_frontend.h"
@@ -1185,8 +1184,6 @@ RTLIL::Design::~Design()
{
for (auto &pr : modules_)
delete pr.second;
for (auto n : bindings_)
delete n;
RTLIL::Design::get_all_designs()->erase(hashidx_);
}
@@ -1226,12 +1223,6 @@ RTLIL::Module *RTLIL::Design::top_module() const
return module_count == 1 ? module : nullptr;
}
void RTLIL::Design::add(RTLIL::Binding *binding)
{
log_assert(binding != nullptr);
bindings_.push_back(binding);
}
RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
{
if (modules_.count(name) != 0)
@@ -1531,8 +1522,6 @@ RTLIL::Module::~Module()
delete pr.second;
for (auto &pr : processes)
delete pr.second;
for (auto binding : bindings_)
delete binding;
#ifdef YOSYS_ENABLE_PYTHON
RTLIL::Module::get_all_modules()->erase(hashidx_);
#endif
@@ -2892,12 +2881,6 @@ void RTLIL::Module::add(RTLIL::Process *process)
process->module = this;
}
void RTLIL::Module::add(RTLIL::Binding *binding)
{
log_assert(binding != nullptr);
bindings_.push_back(binding);
}
void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
{
log_assert(refcount_wires_ == 0);
kernel/rtlil.h
-6
View File
@@ -122,7 +122,6 @@ namespace RTLIL
struct MemWriteAction;
struct SyncRule;
struct Process;
struct Binding;
struct IdString;
struct OwningIdString;
@@ -1902,7 +1901,6 @@ struct RTLIL::Design
int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
std::unique_ptr<define_map_t> verilog_defines;
@@ -1924,7 +1922,6 @@ struct RTLIL::Design
}
void add(RTLIL::Module *module);
void add(RTLIL::Binding *binding);
RTLIL::Module *addModule(RTLIL::IdString name);
void remove(RTLIL::Module *module);
@@ -2078,7 +2075,6 @@ public:
dict<RTLIL::IdString, RTLIL::Cell*> cells_;
std::vector<RTLIL::SigSig> connections_;
std::vector<RTLIL::Binding*> bindings_;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
@@ -2166,8 +2162,6 @@ public:
int cells_size() const { return cells_.size(); }
RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; }
void add(RTLIL::Binding *binding);
// Removing wires is expensive. If you have to remove wires, remove them all at once.
void remove(const pool<RTLIL::Wire*> &wires);
void remove(RTLIL::Cell *cell);
pyosys/generator.py
-1
View File
@@ -136,7 +136,6 @@ global_denylist = frozenset(
)
pyosys_headers = [
# Headers for incomplete types
PyosysHeader("kernel/binding.h"),
PyosysHeader("libs/sha1/sha1.h"),
# Headers for globals
PyosysHeader("kernel/log.h"),
tests/Makefile
-1
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@@ -29,7 +29,6 @@ MK_TEST_DIRS += ./arch/nexus
MK_TEST_DIRS += ./arch/quicklogic/pp3
MK_TEST_DIRS += ./arch/quicklogic/qlf_k6n10f
MK_TEST_DIRS += ./arch/xilinx
MK_TEST_DIRS += ./bind
MK_TEST_DIRS += ./bugpoint
MK_TEST_DIRS += ./opt
MK_TEST_DIRS += ./sat
tests/bind/basic.sv
-20
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@@ -1,20 +0,0 @@
// A basic example of the bind construct
module foo (input logic a, input logic b, output logic c);
// Magic happens here...
endmodule
module bar (input a, input b, output c);
assign c = a ^ b;
endmodule
module top ();
logic u, v, w;
foo foo_i (.a (u), .b (v), .c (w));
bind foo bar bound_i (.*);
always_comb begin
assert(w == u ^ v);
end
endmodule
tests/bind/basic.ys
-1
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@@ -1 +0,0 @@
read_verilog -sv basic.sv
tests/bind/cell_list.sv
-26
View File
@@ -1,26 +0,0 @@
// An example of specifying multiple bind instances in a single directive. This
// also uses explicit bound names.
module foo (input logic a0, input logic b0, output logic c0,
input logic a1, input logic b1, output logic c1);
// Magic happens here...
endmodule
module bar (input a, input b, output c);
assign c = a ^ b;
endmodule
module top ();
logic u0, v0, w0;
logic u1, v1, w1;
foo foo0 (.a0 (u0), .b0 (v0), .c0 (w0),
.a1 (u1), .b1 (v1), .c1 (w1));
bind foo bar bar0 (.a(a0), .b(b0), .c(c0)), bar1 (.a(a1), .b(b1), .c(c1));
always_comb begin
assert(w0 == u0 ^ v0);
assert(w1 == u1 ^ v1);
end
endmodule
tests/bind/cell_list.ys
-1
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@@ -1 +0,0 @@
read_verilog -sv cell_list.sv
tests/bind/generate_mk.py
-8
View File
@@ -1,8 +0,0 @@
#!/usr/bin/env python3
import sys
sys.path.append("..")
import gen_tests_makefile
gen_tests_makefile.generate(["--yosys-scripts"])
tests/bind/hier.sv
-20
View File
@@ -1,20 +0,0 @@
// An example of the bind construct using a hierarchical reference starting with $root
module foo (input logic a, input logic b, output logic c);
// Magic happens here...
endmodule
module bar (input a, input b, output c);
assign c = a ^ b;
endmodule
module top ();
logic u, v, w;
foo foo_i (.a (u), .b (v), .c (w));
always_comb begin
assert(w == u ^ v);
end
endmodule
bind $root.top.foo_i bar bound_i (.*);
tests/bind/hier.ys
-1
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@@ -1 +0,0 @@
read_verilog -sv hier.sv
tests/bind/inst_list.sv
-24
View File
@@ -1,24 +0,0 @@
// An example of specifying multiple bind targets with an instance list
module foo (input logic a, input logic b, output logic c);
// Magic happens here...
endmodule
module bar (input a, input b, output c);
assign c = a ^ b;
endmodule
module top ();
logic u0, v0, w0;
logic u1, v1, w1;
foo foo0 (.a (u0), .b (v0), .c (w0));
foo foo1 (.a (u1), .b (v1), .c (w1));
bind foo : foo0, foo1 bar bound_i (.*);
always_comb begin
assert(w0 == u0 ^ v0);
assert(w1 == u1 ^ v1);
end
endmodule
tests/bind/inst_list.ys
-1
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@@ -1 +0,0 @@
read_verilog -sv inst_list.sv
tests/bind/param.sv
-26
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@@ -1,26 +0,0 @@
// An example showing how parameters get inferred when binding
module foo (input logic a, input logic b, output logic c);
parameter doit = 1;
// Magic happens here...
endmodule
module bar (input a, input b, output c);
parameter doit = 1;
assign c = doit ? a ^ b : 0;
endmodule
module top (input u0, input v0, output w0,
input u1, input v1, output w1);
foo #(.doit (0)) foo0 (.a (u0), .b (v0), .c (w0));
foo #(.doit (1)) foo1 (.a (u1), .b (v1), .c (w1));
bind foo bar #(.doit (doit)) bound_i (.*);
always_comb begin
assert (w0 == '0);
assert (w1 == u1 ^ v1);
end
endmodule
tests/bind/param.ys
-1
View File
@@ -1 +0,0 @@
read_verilog -sv param.sv
tests/bind/toplevel.sv
-20
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@@ -1,20 +0,0 @@
// The bind construct occurring at top-level in the script
module foo (input logic a, input logic b, output logic c);
// Magic happens here...
endmodule
module bar (input a, input b, output c);
assign c = a ^ b;
endmodule
module top ();
logic u, v, w;
foo foo_i (.a (u), .b (v), .c (w));
always_comb begin
assert(w == u ^ v);
end
endmodule
bind top.foo_i bar bound_i (.*);
tests/bind/toplevel.ys
-1
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@@ -1 +0,0 @@
read_verilog -sv toplevel.sv