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Commit Graph
2674 Commits
Author SHA1 Message Date
Emil J. Tywoniak f925de7dc4 techlibs, ffinit: signorm fixes 2026-09-18 17:37:03 +02:00
Emil J. Tywoniak df2ea7d788 memory: declare blackbox ports for generated RAM cells 2026-09-18 17:29:46 +02:00
Emil J. Tywoniak 8917baea67 Revert "intel: register bram celltypes" 
This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.
 2026-09-17 15:43:55 +02:00
Emil J. Tywoniak 987e7ef633 xilinx_dsp: signorm compatibility 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 27b0e2e914 pmgen: hold sigmap pointer instead of owning it 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak d48be905be intel: register bram celltypes 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak d2c99efa2a gowin: replace positional arguments in cells_sim.v with named 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 6c048fdfb9 signorm: disable in passes that use swap_names 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 2ccfd2b23b synth_ice40: always read abc9 model to understand port direction 2026-09-17 14:13:55 +02:00
Lofty 030e13569c synth_gatemate: remove classic ABC mapping for LUTs 2026-08-20 09:33:47 +01:00
Lofty 4cb0a5e2f2 synth: remove classic ABC mapping for LUTs 2026-08-19 11:43:00 +01:00
Lofty 1f72d02f39 synth_microchip: remove classic ABC mapping 2026-08-19 11:43:00 +01:00
Lofty ee75cd3ea0 synth_lattice: remove classic ABC mapping 2026-08-19 11:43:00 +01:00
Lofty dd4b6689e8 synth_intel: remove classic ABC mapping 2026-08-19 11:43:00 +01:00
Lofty 3a148d7633 synth_gowin: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 737560c471 synth_fabulous: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 5fe16f60f9 synth_efinix: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 6df15312cc synth_anlogic: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 873bed6300 synth_achronix: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 63fbb31921 synth_sf2: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 8a01ff15f4 synth_quicklogic: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 6824ee065a synth_nanoxplore: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty c053706540 synth_analogdevices: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 086cd8e685 synth_xilinx: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 44bab117d7 synth_ice40: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty fc6433bbae Merge pull request #6132 from YosysHQ/lofty/abc-refactor-12 
synth_greenpak4, nlutmap: remove
 2026-08-19 10:19:14 +00:00
Lofty edb411a622 synth_greenpak4, nlutmap: remove 2026-08-19 10:56:16 +01:00
Lofty 541d240930 synth_coolrunner2: remove 2026-08-18 10:04:45 +01:00
nick bd90d0e83a cmp2lut techmap fix 2026-08-14 10:17:30 -06:00
nella 7f5b7aacb9 Count module output ports as consumers. 2026-08-12 10:00:30 +02:00
Catherine 1277640bdf CMake: add missing dependency edges for synth_* passes. 2026-08-06 14:48:56 +00:00
nella 511017acc1 Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
nella 526ab7aab3 Use Nexus DSP pipelined registers. 2026-07-24 12:10:07 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
drewbabel 3006280d70 xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
myrtle a0fbe6e133 Merge pull request #6054 from YosysHQ/gatecat/nexus-radiant-fix 
nexus: Fix Radiant netlist compatibility
 2026-07-19 13:22:46 +00:00
gatecat 15c54ae15e nexus: Fix Radiant netlist compatibility 
Signed-off-by: gatecat <[email protected]>
 2026-07-19 12:44:40 +02:00
Johan Olby 63457de80e mul2dsp: normalize operand order 
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
 2026-07-15 16:21:07 +02:00
nella 388ed215c4 Remove old techmap. 2026-07-08 12:07:58 +02:00
nella fe1ce9e5c1 Fix merge. 2026-07-08 11:54:55 +02:00
nella f5809a7c2c Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
nella 362e828dc2 Simplify check -latchonly calls in synth. 2026-07-07 10:10:00 +02:00
Leo Moser b06c57b2bf fabulous: remove unused -blif option 
Signed-off-by: Leo Moser <[email protected]>
 2026-07-01 13:38:45 +02:00
Leo Moser 655cb40d0f fabulous: add --cells-map option 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:51 +02:00
Leo Moser 4fac567673 fabulous: add -arith-map option 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:51 +02:00
Leo Moser d50999ea45 fabulous: format using clang 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:51 +02:00
Leo Moser 2535504217 fabulous: update CMakeLists.txt 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:51 +02:00
Leo Moser aa84f4a13b fabulous: remove legacy arith_map.v mapping 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:51 +02:00
Leo Moser f79c0ad214 fabulous: add -multiplier-map option, map to $__FABULOUS_MUL 
- an example: `-multiplier-map multiplier_map.v 8:8:2:2:10`

Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:44 +02:00
Leo Moser d72cca2945 fabulous: add -clkbuf-map option, map to $__FABULOUS_GBUF 
Signed-off-by: Leo Moser <[email protected]>
 2026-06-30 16:09:33 +02:00