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techlibs, ffinit: signorm fixes

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This commit is contained in:
Emil J. Tywoniak
2026-09-18 17:37:03 +02:00
parent df2ea7d788
commit f925de7dc4
3 changed files with 44 additions and 7 deletions
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kernel/ffinit.h
+6 -4
View File
@@ -53,12 +53,14 @@ struct FfInitVals
if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
continue;
if (initbits.count(bit)) {
if (initbits.at(bit).first != val)
auto found = initbits.find(bit);
if (found != initbits.end()) {
if (found->second.first == val || val == State::Sx)
continue;
if (found->second.first != State::Sx)
log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
log_signal(bit), log_signal(SigBit(wire, i)),
log_signal(val), log_signal(initbits.at(bit).first));
continue;
log_signal(val), log_signal(found->second.first));
}
initbits[bit] = std::make_pair(val,SigBit(wire,i));
techlibs/common/mul2dsp.v
+32
View File
@@ -49,6 +49,38 @@ $fatal(1, "Macro DSP_NAME must be defined");
`define MAX(a,b) (a > b ? a : b)
`define MIN(a,b) (a < b ? a : b)
(* blackbox *)
module \$__mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
endmodule
(* blackbox *)
module \$__soft_mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
endmodule
(* techmap_celltype = "$mul $__mul" *)
module _80_mul (A, B, Y);
parameter A_SIGNED = 0;
techlibs/ice40/ice40_opt.cc
+6 -3
View File
@@ -138,16 +138,19 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
cell->setPort(ID::Y, cell->getPort(ID::O));
RTLIL::SigSpec sig_a { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) };
RTLIL::SigSpec sig_y = cell->getPort(ID::O);
cell->unsetPort(ID::A);
cell->unsetPort(ID::B);
cell->unsetPort(ID::CI);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I3));
cell->unsetPort(ID::CO);
cell->unsetPort(ID::O);
cell->type = ID($lut);
cell->setPort(ID::A, std::move(sig_a));
cell->setPort(ID::Y, std::move(sig_y));
cell->setParam(ID::WIDTH, 4);
cell->unsetParam(ID(I3_IS_CI));
}